We-quatro: Radiation-hardened SRAM cell with parametric process variation tolerance
JS Kim, IJ Chang - IEEE Transactions on Nuclear Science, 2017 - ieeexplore.ieee.org
Under radiation environment, conventional SRAMs suffer from high soft-error rate. To
address this challenge, several radiation-hardened static-random access-memory (SRAM) …
address this challenge, several radiation-hardened static-random access-memory (SRAM) …
Evaluation and mitigation of radiation-induced soft errors in graphics processing units
Graphics processing units (GPUs) are increasingly attractive for both safety-critical and High-
Performance Computing applications. GPU reliability is a primary concern for both the …
Performance Computing applications. GPU reliability is a primary concern for both the …
Efficient majority logic fault detection with difference-set codes for memory applications
SF Liu, P Reviriego, JA Maestro - IEEE transactions on very …, 2010 - ieeexplore.ieee.org
Nowadays, single event upsets (SEUs) altering digital circuits are becoming a bigger
concern for memory applications. This paper presents an error-detection method for …
concern for memory applications. This paper presents an error-detection method for …
DEC ECC design to improve memory reliability in sub-100nm technologies
R Naseer, J Draper - 2008 15th IEEE International Conference …, 2008 - ieeexplore.ieee.org
Exacerbated SRAM reliability issues, due to soft errors and increased process variations in
sub-100 nm technologies, limit the efficacy of conventionally used error correcting codes …
sub-100 nm technologies, limit the efficacy of conventionally used error correcting codes …
Single event effects: Mechanisms and classification
R Gaillard - Soft errors in modern electronic systems, 2010 - Springer
Abstract Single Event Effects (SEEs) induced by heavy ions, protons, and neutrons become
an increasing limitation of the reliability of electronic components, circuits, and systems, and …
an increasing limitation of the reliability of electronic components, circuits, and systems, and …
HARP: Practically and effectively identifying uncorrectable errors in memory chips that use on-die error-correcting codes
Aggressive storage density scaling in modern main memories causes increasing error rates
that are addressed using error-mitigation techniques. State-of-the-art techniques for …
that are addressed using error-mitigation techniques. State-of-the-art techniques for …
End-to-end error correction and online diagnosis for on-chip networks
S Shamshiri, A Ghofrani… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
We propose a comprehensive solution for end-to-end (e2e) error correction and online
defect diagnosis for on-chip networks. For e2e error correction, we propose an interleaved …
defect diagnosis for on-chip networks. For e2e error correction, we propose an interleaved …
A low-voltage radiation-hardened 13T SRAM bitcell for ultralow power space applications
L Atias, A Teman, R Giterman… - … Transactions on Very …, 2016 - ieeexplore.ieee.org
Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power
applications, increases the susceptibility of VLSI circuits to soft-errors, especially when …
applications, increases the susceptibility of VLSI circuits to soft-errors, especially when …
Extending 3-bit burst error-correction codes with quadruple adjacent error correction
J Li, P Reviriego, L Xiao… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
The use of error-correction codes (ECCs) with advanced correction capability is a common
system-level strategy to harden the memory against multiple bit upsets (MBUs). Therefore …
system-level strategy to harden the memory against multiple bit upsets (MBUs). Therefore …
[图书][B] Gain-cell Embedded DRAMs for Low-power VLSI Systems-on-chip
Gain-Cell eDRAM (GC-eDRAM) is an interesting, high-density alternative to SRAM and
conventional 1T-1C eDRAM for a large range of VLSI system-onchip (SoC) applications …
conventional 1T-1C eDRAM for a large range of VLSI system-onchip (SoC) applications …