A 0.9 V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology
A Mishra, A Grover - … Symposium on VLSI Design and Test …, 2020 - ieeexplore.ieee.org
A low Vmin, 6T SRAM is designed in 65nm LSTP (low standby power) technology using
read and write assist schemes. In this work, we reduced the Vmin of SRAM cell from 1.2 V to …
read and write assist schemes. In this work, we reduced the Vmin of SRAM cell from 1.2 V to …
Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations
P Sharma, AK Gundu… - 2016 20th International …, 2016 - ieeexplore.ieee.org
Process variations have become a major challenge with the advancement in CMOS
technologies. The performance of memory sub-systems such as Static Random Access …
technologies. The performance of memory sub-systems such as Static Random Access …
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test-28nm FDSOI implementation
With emerging deep submicron technology, device variations limit the SRAM performance
and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell among …
and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell among …
Yield estimation of SRAM and design of a dual functionality read-write driver for SRAM
P Sharma, MS Hashmi - 2016 - repository.iiitd.edu.in
On chip process parameter variations have become a major challenge to meet the high
density demands and the advancement in CMOS technologies. Variations in threshold …
density demands and the advancement in CMOS technologies. Variations in threshold …