Feedback-based low-power soft-error-tolerant design for dual-modular redundancy
Y Li, Y Li, H Jie, J Hu, F Yang, X Zeng… - … Transactions on Very …, 2018 - ieeexplore.ieee.org
Triple-modular redundancy (TMR), which consists of three identical modules and a voting
circuit, is a common architecture for soft-error tolerance. However, the original TMR suffers …
circuit, is a common architecture for soft-error tolerance. However, the original TMR suffers …
Anti-interference low-power double-edge triggered flip-flop based on C-elements
Z Huang, X Yang, T Song, H Qi… - Tsinghua Science …, 2021 - ieeexplore.ieee.org
When the input signal has been interfered and glitches occur, the power consumption of
Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce …
Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce …
Low Power CMOS Based Dual Edge Triggered Flip Flop Using LECTOR C-Element
A Rawat, M Kumar - 2024 International Conference on …, 2024 - ieeexplore.ieee.org
In the presence of signal interference and glitches, Double-Edge Triggered Flip-Flops
(DETFFs) experience a substantial rise in power consumption. To address this issue and …
(DETFFs) experience a substantial rise in power consumption. To address this issue and …
Soft-event-upset and soft-event-transient tolerant cmos circuit design for low-voltage low-power wireless IoT applications
IC Wey, CH Chen, SZ Fang… - … Conference on Ubiquitous …, 2019 - ieeexplore.ieee.org
In the wireless IoT applications, low power is a critical criteria, and low-voltage is a direct
way to meet such demand. However, low-voltage criteria in advanced CMOS VLSI designs …
way to meet such demand. However, low-voltage criteria in advanced CMOS VLSI designs …
Soft-error tolerant design in near-threshold-voltage computing
IC Wey, SZ Fang, HJ Chou… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
In the advanced CMOS VLSI designs, lower supply voltage and smaller transistor lead to
critical design challenges in dealing with soft-error interference, especial for the deisgn …
critical design challenges in dealing with soft-error interference, especial for the deisgn …
Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements
Z Huang, W Zhong, L Duan, Y Zhang… - Journal of Circuits …, 2022 - World Scientific
Glitch at the input can increase the power consumption of flip-flop greatly. To solve this
problem effectively, a Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on …
problem effectively, a Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on …
SEU hardened layout design for SRAM cells based on SEU reversal
P Li, W Guo, Z Zhao, M Zhang, Q Deng - IEICE Electronics Express, 2015 - jstage.jst.go.jp
In this paper, the generation mechanism of single event upset reversal (SEUR) between 2
PMOS in SRAM cells is studied in depth based on 45nm CMOS technology. We find that …
PMOS in SRAM cells is studied in depth based on 45nm CMOS technology. We find that …
A SEU Immune Flip-Flop with Low Overhead
Z Huang, X Li, S Pan, M Wang, T Ni - International Conference on …, 2020 - Springer
In nano-scale CMOS technologies, storage cells such as flip-flops are becoming
increasingly sensitive to soft errors caused by harsh radiation effects. This paper proposes a …
increasingly sensitive to soft errors caused by harsh radiation effects. This paper proposes a …
Low-power Error-tolerant Digital Logic Circuit Design
Y Li - 2019 - era.library.ualberta.ca
As semiconductor process minimum linewidths have been scaled down to nanometers,
digital computing circuits have become more and more complex. Meanwhile, these …
digital computing circuits have become more and more complex. Meanwhile, these …