STRAIGHT: Hazardless processor architecture without register renaming

H Irie, T Koizumi, A Fukuda, S Akaki… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
The single-thread performance of a processor improves the capability of the entire system by
reducing the critical path latency of programs. Typically, conventional superscalar …

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors

T Koizumi, R Shioya, S Sugita, T Amano… - Proceedings of the 56th …, 2023 - dl.acm.org
Out-of-order superscalar processors are currently the only architecture that speeds up
irregular programs, but they suffer from poor power efficiency. To tackle this issue, we …

Compiling and optimizing real-world programs for STRAIGHT ISA

T Koizumi, S Sugita, R Shioya… - 2021 IEEE 39th …, 2021 - ieeexplore.ieee.org
The renaming unit of a superscalar processor is a very expensive module. It consumes large
amounts of power and limits the front-end bandwidth. To overcome this problem, an …

Enhancing GPU Performance through Complexity-Effective Out-of-Order Execution using Distance-based ISA

R MATSUO, T KOIZUMI, H IRIE, S SAKAI… - IEICE Transactions on …, 2024 - jstage.jst.go.jp
Graphics processing units (GPUs) have been introduced in various fields due to their high
parallel computing performance. A key feature of GPUs is multi-threaded execution, where a …

TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA

R Matsuo, T Koizumi, H Irie, S Sakai… - IEEE Computer …, 2023 - ieeexplore.ieee.org
A graphics processing unit (GPU) is a processor that achieves high throughput by exploiting
data parallelism. We found that many GPU workloads also contain instruction-level …

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA

S Sugita, T Koizumi, R Shioya, H Irie… - Proceedings of the 32nd …, 2023 - dl.acm.org
The single-thread performance of a processor core is essential even in the multicore era.
However, increasing the processing width of a core to improve the single-thread …

Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme

S Zhou, H Wang, D Tong - Proceedings of the 26th Asia and South …, 2021 - dl.acm.org
Register renaming is the key for the performance of out-of-order processors. However, the
release mechanism of the physical register may cause a waste from time dimension. The …

An Inductive Method to Select Simulation Points

M Choi, T Fukuda, M Goshima… - IEICE TRANSACTIONS on …, 2016 - search.ieice.org
The time taken for processor simulation can be drastically reduced by selecting simulation
points, which are dynamic sections obtained from the simulation result of processors. The …

Pipelined Serial Register Renaming

D Spasov - ICT Innovations 2020. Machine Learning and …, 2020 - Springer
Superscalar microarchitectures include register renaming units where architectural registers
are renamed to physical registers. Modern renaming units are required to rename more than …

Sequential Register Renaming

D Spasov - 2020 43rd International Convention on Information …, 2020 - ieeexplore.ieee.org
Register renaming unit is a bottleneck in the superscalar cores because it limits the number
of instructions and the number of threads that may concurrently be processed. We propose a …