A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration
M Gupta, BS Song - IEEE Journal of Solid-State Circuits, 2006 - ieeexplore.ieee.org
A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase
noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog …
noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog …
Prediction of Phase Noise and Spurs in a Nonlinear Fractional- Frequency Synthesizer
Y Donnelly, MP Kennedy - … on Circuits and Systems I: Regular …, 2019 - ieeexplore.ieee.org
Integer boundary spurs appear in the passband of the loop response of fractional-N phase
lock loops and are, therefore, a potentially significant component of the phase noise. In spite …
lock loops and are, therefore, a potentially significant component of the phase noise. In spite …
Fractional-N frequency synthesis: overview and practical aspects with FIR-embedded design
This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical
design perspectives focusing on a ${\Delta}{\Sigma} $ modulation technique and a finite …
design perspectives focusing on a ${\Delta}{\Sigma} $ modulation technique and a finite …
A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise
SE Meninger, MH Perrott - … on Circuits and Systems II: Analog …, 2003 - ieeexplore.ieee.org
Techniques are proposed to dramatically reduce the impact of quantization noise in/spl
Sigma//spl Delta/fractional-N synthesizers, thereby improving the existing tradeoff between …
Sigma//spl Delta/fractional-N synthesizers, thereby improving the existing tradeoff between …
Comparison frequency doubling and charge pump matching techniques for dual-band/spl Delta//spl Sigma/fractional-N frequency synthesizer
H Huh, Y Koo, KY Lee, Y Ok, S Lee… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS
technology. In supporting dual bands, all building blocks except VCOs are shared. A current …
technology. In supporting dual bands, all building blocks except VCOs are shared. A current …
A PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology
CY Yang, CH Chang, WG Wong - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
A triangular-modulated spread-spectrum clock generator using a Delta-Sigma-modulated
fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to …
fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to …
4.48-GHz Fractional- Frequency Synthesizer With Spurious-Tone Suppression via Probability Mass Redistribution
Y Donnelly, MP Kennedy, J Breslin… - IEEE Solid-State …, 2019 - ieeexplore.ieee.org
A 4.48-GHz type-II charge pump fractional-N PLL implemented in a 0.18-μm BiCMOS
process is presented. The divider controller's output is processed using a novel block, the …
process is presented. The divider controller's output is processed using a novel block, the …
A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops
L Zhang, X Yu, Y Sun, W Rhee, D Wang… - IEEE journal of solid …, 2009 - ieeexplore.ieee.org
A finite-modulo fractional-N PLL utilizing a low-bit high-order DeltaSigma modulator is
presented. A 4-bit fourth-order DeltaSigma modulator not only performs non-dithered 16 …
presented. A 4-bit fourth-order DeltaSigma modulator not only performs non-dithered 16 …
A 0.77 ps RMS jitter 6-GHz spread-spectrum clock generator using a compensated phase-rotating technique
KH Cheng, CL Hung, CH Chang - IEEE journal of solid-state …, 2011 - ieeexplore.ieee.org
This study demonstrates a 6-GHz triangular-modulated spread-spectrum clock generator
(SSCG) based on a fractional-N PLL in a 90-nm CMOS process. This paper presents a …
(SSCG) based on a fractional-N PLL in a 90-nm CMOS process. This paper presents a …
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
T Lee, IN Hajj, EM Rudnick… - Proceedings of 14th VLSI …, 1996 - ieeexplore.ieee.org
An efficient automatic test pattern generator for I/sub DDQ/current testing of CMOS digital
circuits is presented. The complete two-line bridging fault set is considered. An adaptive …
circuits is presented. The complete two-line bridging fault set is considered. An adaptive …