ILP-based modulo scheduling and binding for register minimization

P Sittel, M Kumm, J Oppermann… - … conference on field …, 2018 - ieeexplore.ieee.org
A key element for achieving high throughput, eg circuits generated with high-level synthesis
(HLS) methods and model-based hardware design, is the use of modulo scheduling. Integer …

[图书][B] Run-time Reconfigurable Constant Multiplication on Field Programmable Gate Arrays

K Möller - 2017 - books.google.com
This book addresses the question how run-time reconfigurable constant multipliers (RCMs)
can be efficiently implemented on field programmable gate arrays (FPGAs). RCMs calculate …

Model-based hardware design based on compatible sets of isomorphic subgraphs

P Sittel, K Möller, M Kumm, P Zipf… - … Conference on Field …, 2017 - ieeexplore.ieee.org
Hardware applications in an industrial context often have tight area, latency and throughput
requirements or a specific combination thereof. This paper presents a method to improve …

Automatic hardware design tool based on reusing transformation

C Fang, Z Zhang, X You… - 2019 IEEE 13th …, 2019 - ieeexplore.ieee.org
Automatic hardware design is currently drawing research attentions as it has the potential to
free designers from low level manual design process. In this paper, we propose an …

Réseaux de Petri temporisés pour la synthèse de circuits pipelinés

R Parrot - 2022 - theses.hal.science
Dans cette thèse, nous nous intéressons à l'optimisation des ressources consommées par
un circuit implémentant une loi de commande pour la charge de véhicules électriques sur …