Means to Accelerate Transfer of Information Between Integrated Circuits
V Melikyan - Machine Learning-based Design and Optimization of …, 2023 - Springer
This chapter is devoted to the development of means in I/O blocks that will allow to increase
the frequency of the transmitted signal and to level the distorted signal. Effective approaches …
the frequency of the transmitted signal and to level the distorted signal. Effective approaches …
A 10-Gb/s Single-Loop Half-Rate DLL-Based Clock and Data Recovery Circuit for Forwarded-Clock Wireline Transceivers
AK Mohamed, SA Ibrahim… - Mansoura …, 2024 - mej.researchcommons.org
This paper introduces a 10-Gb/s single-loop, half-rate delay-locked loop (DLL)-based clock
and data recovery (CDR) circuit for forwarded-clock (FC) wireline transceivers. The …
and data recovery (CDR) circuit for forwarded-clock (FC) wireline transceivers. The …