Recent studies on noisy decoding for LDPC codes rely on the assumption that the noise in
each component is independent and perpetual. This paper examines a noisy decoding …

This paper introduces a novel concept for exploiting low-power edge graphics processing
units (GPUs) for decoding higher-order non-binary low-density parity-check (LDPC) codes …

A system and method for double data rate (DDR) chip-kill decoding using an array of ECC
erasure decoders operating in parallel to identify a location of a chip-kill event associated …

Communication systems have been associated with an inherent fault tolerance to hardware
reliability issues. Therefore, many publications have studied the impact of such issues on, for …

Flash memory devices are increasingly being used in deep-space missions as on-board
data storage in spacecraft. The harsh environment these missions take place in involves …

Technology scaling has progressed to enable integrated circuits with extremely high density
enabling systems of tremendous complexity with manageable power consumption. With the …

In this paper, we perform a simulated fault injection reliability assessment of memory centric
flooded LDPC decoders affected by probabilistic storage errors. We investigate the error …

Os códigos definidos por matrizes de teste de paridade esparsas (LDPC) são bastante em
sistemas de comunicação digital e armazenamento de dados, por operarem quase à …

A method and apparatus for decoding in which a first failed decode operation is performed
on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to …

A method for meeting quality of service (QoS) requirements in a flash controller that includes
one or more instruction queues and a neural network engine. A configuration file for a QoS …