An apparatus comprises field-effect transistor (FET) structures stacked horizontally and
vertically in a three-dimensional memory array architecture, gates extending vertically and …

Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-
crystalline silicon semicon ductor vertical NAND channel. Memory holes are formed in …

A nonvolatile memory device includes a conductive line disposed on a substrate and
vertically extended from the substrate, a first channel layer disposed on the substrate and …

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …

Some embodiments include apparatuses and methods using first and second select gates
coupled in series between a conductive line and a first memory cell string of a memory …

Disclosed herein are 3D stacked memory devices having WL select gates that comprises
TFTs having bodies formed from a wide band gap semiconductor. The wide energy band …

An apparatus comprises field-effect transistor (FET) struc tures stacked horizontally and
vertically in a three-dimen sional memory array architecture, gates extending vertically and …

H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …

An apparatus comprises field-effect transistor (FET) struc tures stacked horizontally and
vertically in a three-dimen sional memory array architecture, gates extending vertically and …