Single bit‐line 11T SRAM cell for low power and improved stability

R Lorenzo, R Pailly - IET Computers & Digital Techniques, 2020 - Wiley Online Library
This study aims for a new 11T static random access memory (SRAM) cell that uses power
gating transistors and transmission gate for low leakage and reliable write operation. The …

A 0.7-v 17.4-/spl mu/w 3-lead wireless ecg soc

M Khayatzadeh, X Zhang, J Tan… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
This paper presents a fully integrated sub-1 V 3-lead wireless ECG System-on-Chip (SoC)
for wireless body sensor network applications. The SoC includes a two-channel ECG front …

Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory

S Lee, G Park, H Jeong - Sensors, 2023 - mdpi.com
This paper comparatively reviews sensing circuit designs for the most widely used
embedded memory, static random-access memory (SRAM). Many sensing circuits for SRAM …

Bit-interleaving-enabled 8T SRAM with shared data-aware write and reference-based sense amplifier

L Wen, X Cheng, K Zhou, S Tian… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This brief proposes the design of a low-voltage static random access memory (SRAM) for
biomedical chip applications. The SRAM is designed using a standard 8T bit cell, featuring a …

[PDF][PDF] A comprehensive review of design challenges and techniques for nanoscale SRAM: a cell perspective

S Ahmad, N Alam, M Hasan, BS Kong - Authorea Preprints, 2022 - techrxiv.org
In order to meet the ultra-low power requirement of modern digital systems, voltage scaling
is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled …

Radiation hardened 12T SRAM with crossbar-based peripheral circuit in 28nm CMOS technology

Y Han, T Li, X Cheng, L Wang, J Han… - … on Circuits and …, 2021 - ieeexplore.ieee.org
Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm
technology due to the scaling of the transistors. High soft error rate is caused by particle …

A 16-kb 9T ultralow-voltage SRAM with column-based split cell-VSS, data-aware write-assist, and enhanced read sensing margin in 28-nm FDSOI

MSM Siddiqui, ZC Lee, TTH Kim - IEEE Transactions on Very …, 2021 - ieeexplore.ieee.org
This work proposes an static random access memory (SRAM) with column-based split cell-
VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28 …

Memory device

J Seongook, K Kyoman, H Jeong, YH Yang… - US Patent …, 2017 - Google Patents
Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-
coupled inverter and pass gate transistor connected to data storage node of the cross …

Full-swing local bitline SRAM architecture based on the 22-nm FinFET technology for low-voltage operation

K Kang, H Jeong, Y Yang, J Park… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
The previously proposed average-8T static random access memory (SRAM) has a
competitive area and does not require a write-back scheme. In the case of an average-8T …

Certain investigations in achieving low power dissipation for SRAM cell

N Deepak, RB Kumar - Microprocessors and Microsystems, 2020 - Elsevier
The modern semiconductor industry is evolving quite rapidly. Portable and mobile devices
are becoming smaller every day and there is also a growing demand for longer battery …