Flip chip semiconductor die internal signal access system and method

BS Schieck, HL Marks - US Patent 8,357,931, 2013 - Google Patents
5,880,592 5,907,562 5,913,034 5,966,021 5.996, 099 6,011,748 6,049,900 6,056,784
6,057,698 6,081.429 6,085.346 6,097,087 6,114,892 6,133,744 6,246,252 6,247,165 …

Storing multicore chip test data

M Seuring - US Patent 7,673,208, 2010 - Google Patents
US7673208B2 - Storing multicore chip test data - Google Patents US7673208B2 - Storing
multicore chip test data - Google Patents Storing multicore chip test data Download PDF Info …

Implementing hierarchical design-for-test logic for modular circuit design

R Kapur, A Chandra, Y Kanzawa, J Saikia - US Patent 8,065,651, 2011 - Google Patents
RSPONSEWECTOR 720 input signal to the DFT circuitry of a second module, such that the
bit sequence can include a set of control signal values for controlling the DFT circuitry, and …

Distributed test compression for integrated circuits

B Foutz, P Gallagher, V Chickermane… - US Patent …, 2011 - Google Patents
(57) ABSTRACT A method for testing integrated circuits is provided. The method provides for
incorporating compression and decom pression logic into each sub-component of an …

Granular dynamic test systems and methods

M Sonawane, A Sanghani, JE Colburn… - US Patent …, 2020 - Google Patents
In one embodiments, a system comprises: a plurality of scan test chains configured to
perform test operations at a first clock speed; a central test controller for controlling testing by …

Multiple input signature register analysis for digital circuitry

N Maheshwari, W Pradeep, P Narayanan - US Patent 10,184,980, 2019 - Google Patents
(57) ABSTRACT A system includes a multiple input signature register (MISR) to receive
outputs from M different scan chains in response to N test patterns applied to test an …

Integrated circuit for compression mode scan test

LEE Heon-Hee, HJ Lee - US Patent 8,539,293, 2013 - Google Patents
At least one embodiment of the present invention provides a circuit and method that allows a
scantest to be performed on integrated circuits manufactured by different companies using a …

Scheme for masking output of scan chains in test circuit

A Chandra, SB Chebiyam, J Saikia… - US Patent …, 2016 - Google Patents
(57) Operating a scan chain of a test circuit of an integrated circuit to have either a single
fanout or multiple fanout to a compres sor. The test circuit receives a fanout control signal for …

Test partition external input/output interface control for test partitions in a semiconductor

S Chadalavda, S Sarangi, M Sonawane… - US Patent …, 2019 - Google Patents
G06F11/2205—Detection or location of defective computer hardware by testing during
standby operation or during idle time, eg start-up testing using arrangements specific to the …

Process for making an electric testing of electronic devices

A Pagani - US Patent 8,479,066, 2013 - Google Patents
(57) ABSTRACT A process for electrically testing electronic devices includes connecting at
least one electronic device to an automatic testingapparatus Suitable for testing digital …