Physical and chemical mechanisms in oxide-based resistance random access memory
KC Chang, TC Chang, TM Tsai, R Zhang… - Nanoscale research …, 2015 - Springer
In this review, we provide an overview of our work in resistive switching mechanisms on
oxide-based resistance random access memory (RRAM) devices. Based on the …
oxide-based resistance random access memory (RRAM) devices. Based on the …
Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors
WM Weber, T Mikolajick - Reports on Progress in Physics, 2017 - iopscience.iop.org
Research in the field of electronics of 1D group-IV semiconductor structures has attracted
increasing attention over the past 15 years. The exceptional combination of the unique 1D …
increasing attention over the past 15 years. The exceptional combination of the unique 1D …
Monolithically Integrated Enhancement-Mode and Depletion-Mode β-Ga2O3 MESFETs with Graphene-Gate Architectures and Their Logic Applications
J Kim, J Kim - ACS applied materials & interfaces, 2020 - ACS Publications
Ultrawide band gap (UWBG) β-Ga2O3 is a promising material for next-generation power
electronic devices. An enhancement-mode (E-mode) device is essential for designing power …
electronic devices. An enhancement-mode (E-mode) device is essential for designing power …
The junctionless transistor
JP Colinge - Emerging devices for low-power and high …, 2018 - taylorfrancis.com
The junctionless transistor consists of a piece of uniformly doped semiconductor with a gate
placed between the source and drain contacts and is, therefore, the simplest transistor …
placed between the source and drain contacts and is, therefore, the simplest transistor …
Complementary resistive switching behavior induced by varying forming current compliance in resistance random access memory
YT Tseng, TM Tsai, TC Chang, CC Shih… - Applied Physics …, 2015 - pubs.aip.org
In this study of resistance random access memory in a resistive switching film, the
breakdown degree was controlled by varying forming current compliance. A SiO x layer was …
breakdown degree was controlled by varying forming current compliance. A SiO x layer was …
Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates
TY Liu, FM Pan, JT Sheu - IEEE Journal of the Electron Devices …, 2015 - ieeexplore.ieee.org
A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire
(poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate …
(poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate …
Effects of varied negative stop voltages on current self-compliance in indium tin oxide resistance random access memory
CY Lin, KC Chang, TC Chang, TM Tsai… - IEEE Electron …, 2015 - ieeexplore.ieee.org
We have previously investigated the automatic current compliance property for indium tin
oxide (ITO) resistance random access memory (RRAM). Traditionally, for the purpose of …
oxide (ITO) resistance random access memory (RRAM). Traditionally, for the purpose of …
Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)
V Thirunavukkarasu, YR Jhan, YB Liu… - Applied Physics …, 2017 - pubs.aip.org
A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with
an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of …
an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of …
Semiconductor devices and methods of manufacture thereof
JP Colinge, CH Diaz, TP Guo - US Patent 9,419,003, 2016 - Google Patents
An SRAM cell includes a first vertical pull-up transistor stacked atop a first vertical pull-down
transistor, and a second vertical pull-up transistor stacked atop a second vertical pull-down …
transistor, and a second vertical pull-up transistor stacked atop a second vertical pull-down …
Junctionless poly-Si nanowire transistors with low-temperature trimming process for monolithic 3-D IC application
JY Lin, PY Kuo, KL Lin, CC Chin… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW)
transistors with gate-all-around configuration and raised source/drain were successfully …
transistors with gate-all-around configuration and raised source/drain were successfully …