A survey of recent advances in SAT-based formal verification

MR Prasad, A Biere, A Gupta - International Journal on Software Tools for …, 2005 - Springer
Dramatic improvements in SAT solver technology over the last decade and the growing
need for more efficient and scalable verification solutions have fueled research in …

Bounded model checking

A Biere - Handbook of satisfiability, 2021 - ebooks.iospress.nl
One of the most important industrial applications of SAT is currently Bounded Model
Checking (BMC). This technique is typically used for formal hardware verification in the …

Model checking and the state explosion problem

EM Clarke, W Klieber, M Nováček, P Zuliani - LASER Summer School on …, 2011 - Springer
Abstract Model checking is an automatic verification technique for hardware and software
systems that are finite state or have finite state abstractions. It has been used successfully to …

SMT-based model checking for recursive programs

A Komuravelli, A Gurfinkel, S Chaki - Formal Methods in System Design, 2016 - Springer
We present an SMT-based symbolic model checking algorithm for safety verification of
recursive programs. The algorithm is modular and analyzes procedures individually. Unlike …

Model checking: algorithmic verification and debugging

EM Clarke, EA Emerson, J Sifakis - Communications of the ACM, 2009 - dl.acm.org
Turing Lecture from the winners of the 2007 ACM AM Turing Award. In 1981, Edmund M.
Clarke and E. Allen Emerson, working in the USA, and Joseph Sifakis working …

Implementing efficient all solutions SAT solvers

T Toda, T Soh - Journal of Experimental Algorithmics (JEA), 2016 - dl.acm.org
All solutions SAT (AllSAT for short) is a variant of the propositional satisfiability problem.
AllSAT has been relatively unexplored compared to other variants despite its significance …

Replication and abstraction: Symmetry in automated formal verification

T Wahl, A Donaldson - Symmetry, 2010 - mdpi.com
This article surveys fundamental and applied aspects of symmetry in system models, and of
symmetry reduction methods used to counter state explosion in model checking, an …

An analysis of SAT-based model checking techniques in an industrial environment

N Amla, X Du, A Kuehlmann, RP Kurshan… - … Hardware Design and …, 2005 - Springer
Abstract Model checking is a formal technique for automatically verifying that a finite-state
model satisfies a temporal property. In model checking, generally Binary Decision Diagrams …

Unbounded protocol compliance verification using interval property checking with invariants

MD Nguyen, M Thalmaier, M Wedler… - … on Computer-Aided …, 2008 - ieeexplore.ieee.org
We propose a methodology to formally prove protocol compliance for communication blocks
in System-on-Chip (SoC) designs. In this methodology, a set of operational properties is …

Advances in 6erilcation of Time Petri Nets and Timed Automata

G ROLA - 2006 - Springer
Verification of real-time systems is an important subject of research. This is highly motivated
by an increasing demand to verify safety critical systems, ie, time-dependent distributed …