Design and analysis of soft error rate in FET/CNTFET based radiation hardened SRAM cell

BR Muthu, EP Pushpa, V Dhandapani, K Jayaraman… - Sensors, 2021 - mdpi.com
Aerospace equipages encounter potential radiation footprints through which soft errors
occur in the memories onboard. Hence, robustness against radiation with reliability in …

Radiation Hardness Study of LG = 20 nm FinFET and Nanowire SRAM Through TCAD Simulation

A Elwailly, J Saltin, MJ Gadlage… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Radiation hardness of FinFET and stacked nanowire (NW) static random-access memory
(SRAM), with LG= 20 nm, which corresponds to high-density 5 nm technology node, is …

Designing and Reliability analysis of radiation hardened Stacked gate Junctionless FinFET and CMOS Inverter

HD Sehgal, Y Pratap, S Kabra - IEEE Transactions on Device …, 2023 - ieeexplore.ieee.org
Along with radiation sensing, necessity to study and design reliable radiation hardened
devices is also increasing now-a-days. These devices are tolerant to high dosage of …

Topological variation on sub-20 nm double-gate inversion and Junctionless-FinFET based 6T-SRAM circuits and its SEU radiation performance

S Nilamani, P Chitra, VN Ramakrishnan - Microelectronics Reliability, 2018 - Elsevier
Introduction of new conduction mechanism called junctionless in MOSFETs takes us to
another direction in device fabrication. Moving from inversion to junctionless devices in …

GaAs junctionless FinFET using high-k dielectric for high-performance applications

A Kumar, A Chhabra, R Chaujar - 2018 IEEE 38th International …, 2018 - ieeexplore.ieee.org
This paper proposes GaAs junctionless (JL)-FinFET for high-performance applications.
Results are so obtained and compared with conventional JL-FinFET. FinFET is designed …

3D double-gate junctionless nanowire transistor-based pass transistor logic circuits for digital applications

A Baidya, TR Lenka, S Baishya - IETE Journal of Research, 2022 - Taylor & Francis
We investigate the circuit performance of the junctionless nanowire transistor. We have
demonstrated pass transistor-based logic gates using the junctionless transistor. Pass …

Study of layout dependent radiation hardness of FinFET SRAM using full domain 3D TCAD simulation

K Huynh, J Saltin, JW Han… - 2019 IEEE SOI-3D …, 2019 - ieeexplore.ieee.org
Due to the emerging of novel technologies, such as stacked horizontal nanowires, and novel
3D integration schemes, such as stacking PMOS on top of NMOS, multiple transistors in a …

GaAs junctionless FinFET Using Si3N4 spacer for high performance analog application

A Chhabra, A Kumar, R Chaujar - … International Conference On …, 2018 - ieeexplore.ieee.org
This paper proposes GaAs junctionless FinFET which is compared with Si and Ge based
junctionless FinFET and shows significant improvement. It is designed using metal gate and …

3D numerical simulations of single-event transient effects in SOI FinFETs

Z Wu, B Zhu, T Yi, C Li, Y Liu, Y Yang - Journal of Computational …, 2018 - Springer
The characteristics and mechanism of single-event transients in silicon-on-insulator (SOI) fin
field-effect transistors (FinFETs) were analyzed using Sentaurus technology computer-aided …

Total ionizing dose effect of gamma rays on H-gate PDSOI MOS devices at different dose rates

QQ Wang, HX Liu, SL Wang, CX Fei, DD Zhao… - Nuclear Science and …, 2017 - Springer
The total dose effect of 60 Co γ-rays on 0.8-μm H-gate partially depleted-silicon-on-insulator
NMOS devices was investigated at different irradiation doses. The results show that the shift …