High-density SRAM read access yield estimation methodology
G Baek, H Jeong - IEEE Access, 2021 - ieeexplore.ieee.org
As high-density SRAMs must be designed to ensure a substantially small failure rate, the
accurate yield estimation with practically acceptable runtime of circuit simulations is highly …
accurate yield estimation with practically acceptable runtime of circuit simulations is highly …
Efficient calculation of uncertainty quantification
EJW Maten, R Pulch, WHA Schilders… - Progress in Industrial …, 2014 - Springer
Abstract We consider Uncertainty Quantification (UQ) by expanding the solution in so-called
generalized Polynomial Chaos expansions. In these expansions the solution is …
generalized Polynomial Chaos expansions. In these expansions the solution is …
Fast time-domain simulation for reliable fault detection
B Tasić, JJ Dohmen, R Janssen… - … , Automation & Test …, 2016 - ieeexplore.ieee.org
Imperfections in manufacturing processes may cause unwanted connections (faults) that are
added to the nominal,“golden”, design of an electronic circuit. By fault simulation we …
added to the nominal,“golden”, design of an electronic circuit. By fault simulation we …
Importance sampling for determining SRAM yield and optimization with statistical constraint
EJW Ter Maten, O Wittich, A Di Bucchianico… - Scientific Computing in …, 2012 - Springer
Importance Sampling allows for efficient Monte Carlo sampling that also properly covers tails
of distributions. From Large Deviation Theory we derive an optimal upper bound for the …
of distributions. From Large Deviation Theory we derive an optimal upper bound for the …
Robust and efficient uncertainty quantification and validation of RFIC isolation
A Di Bucchianico, EJW ter Maten, R Pulch… - …, 2014 - research.tue.nl
Modern communication and identification products impose demanding constraints on
reliability of components. Due to this, statistical constraints more and more enter optimization …
reliability of components. Due to this, statistical constraints more and more enter optimization …
Design of SRAM for CMOS 32nm
L Hamouche - 2011 - theses.hal.science
The PhD thesis focuses on the always-on low power SRAM memories (essentially low
dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the …
dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the …
Method for optimizing sense amplifier timing
EM McCombs, AE Runas, ME Runas - US Patent App. 13/558,976, 2014 - Google Patents
Embodiments of a method are disclosed that may allow for the optimization of a memory
circuit design parameter. The method may include the statistical simulation of one or more …
circuit design parameter. The method may include the statistical simulation of one or more …
Access time optimization of SRAM memory with statistical yield constraint
T Doorn, J ter MATEN, A Di Bucchianico… - Proceedings of 22nd …, 2012 - ieeexplore.ieee.org
A product may fail when design parameters are subject to large deviations. To guarantee
yield one likes to determine bounds on the parameter range such that the fail probability P …
yield one likes to determine bounds on the parameter range such that the fail probability P …
Low power options for 32 nm always-on SRAM architecture
L Hamouche, B Allard - Solid-state electronics, 2011 - Elsevier
The SRAM 6T bit-cell suffers many limitations in advanced technology nodes among which
variability effects. Various alternatives have been experimented and the paper focuses on …
variability effects. Various alternatives have been experimented and the paper focuses on …
Estimating Failure Probabilities
EJW ter Maten, TGJ Beelen, A Di Bucchianico… - Nanoelectronic Coupled …, 2019 - Springer
Abstract System failure describes an undesired configuration of an engineering device,
possibly leading to the destruction of material or a significant loss of performance and a …
possibly leading to the destruction of material or a significant loss of performance and a …