In this study, we introduce a new runtime fault detection technique for systolic array
accelerators oriented to neural network applications. The method exploits the functional path …

Analyzing the SEU-induced Error Propagation in Systolic Array on SRAM-based FPGA Page 1
Analyzing the SEU-induced Error Propagation in Systolic Array on SRAM-based FPGA …

Single Event Transient faults pose an increasing challenge in reliability design especially
regarding internal nodes of combinational voting circuits, as device dimensions shrink and …

This research investigates the crucial integration of Neural Network (NN) models with the
architecture of the hardware (HW) accelerator. Unlike existing approaches overlooking this …

As CNNs gain traction on hardware accelerators, Field Programmable Gate Arrays (FPGAs)
stand out for their flexibility and computational power. However, ensuring the reliability on …

In space applications, the electronic systems that drive mission-critical operations face
unique challenges due to harsh environments characterized by temperature variations and …

As Deep Neural Networks (DNNs) advance, the need for fault-tolerant Neural Processing
Units (NPUs) becomes crucial to prevent system failures in safety-critical applications …

I Field Programmable Gate Arrays (FPGAs) sono circuiti integrati riprogrammabili un numero
indefinito di volte dopo la produzione. Questa caratteristica permette di adattare il …