This paper describes a time-to-digital converter (TDC) with~ 1.2 ps resolution and~ 327 mus
dynamic range suitable for laser range-finding application for example. The resolution of …

A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18/spl mu/m
CMOS technology. In this paper, the design procedure of the new architecture and …

Improving the energy efficiency of computer communication is becoming more and more
important as the world is creating a massive amount of data, while the interface has been a …

The need for low-power high-resolution ADCs in a broad range of emerging applications
and the architecture to realize these ADCs are examined. The pros and cons of various TDC …

A high performance all digital PLL RF synthesizer is presented. The key building block is a
high resolution time to digital converter (TDC) that allows for low in-band phase noise. The …

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is
presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced …

This paper presents a novel multichannel time to digital converter (TDC) specifically
designed for the digitization of photon time of flight (TOF) and energy in positron emission …

A design for an all‐digital high‐resolution pulse‐width modulator (HRPWM) architecture is
presented in this work. The architecture is based on a novel digitally controlled delay …

This paper describes a timing-skew calibration technique which equalizes the phase
spacings among multiphase clocks. The scheme uses simple sample-and-hold circuits …

A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the
multiphase clock generator. The high-speed multiphase clock generator produces a five …