[图书][B] Introduction to microelectronics to nanoelectronics: design and technology

MK Majumder, VR Kumbhare, A Japa, BK Kaushik - 2020 - taylorfrancis.com
Focussing on micro-and nanoelectronics design and technology, this book provides
thorough analysis and demonstration, starting from semiconductor devices to VLSI …

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

A Japa, H Vallabhaneni, R Vaddi - IET Circuits, Devices & …, 2016 - Wiley Online Library
Tunnel field effect transistors (TFETs) have emerged as one of the most promising post‐
CMOS technologies for digital, analogue and RF designs. However, it has been …

Design and performance benchmarking of hybrid tunnel FET/STT-MTJ-based logic in-memory designs for energy efficiency

SV Yamani, NU Rani, R Vaddi - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
With CMOS technology scaling and increased short channel effects, spin-transfer torque-
magnetic tunnel junction (STT-MTJ)/CMOS-based logic-in-memory (LIM) designs consume …

Circuit and architectural co-design for reliable adder cells with steep slope tunnel transistors for energy efficient computing

S Shaik, KSR Krishna, R Vaddi - 2016 29th International …, 2016 - ieeexplore.ieee.org
Tunnel FETs (TFETs) as steep slope devices have attracted much attention for designing
energy efficient digital systems at scaled supply voltages. In this paper, we propose a …

Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

A Japa, MK Majumder, SK Sahoo… - International Journal of …, 2020 - Wiley Online Library
Tunnel field‐effect transistor (TFET) exhibits significant p‐i‐n forward leakage with the
increase in drain‐to‐source voltage bias, and this adversely impacts the power consumption …

Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing

S Shaik - Journal of Circuits, Systems and Computers, 2020 - World Scientific
This paper explores the design and analysis of 20 nm tunnel transistor-based Exclusive-OR
(Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy …

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low V

S Shaik, KSR Krishna, R Vaddi - Journal of Circuits, Systems and …, 2018 - World Scientific
Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent
attention for energy efficient circuit designs with CMOS technology scaling. This paper …

Tunnel transistors with circuit co-design in designing reliable logic gates for energy efficient computing

S Shaik, KSR Krishna, R Vaddi - 2015 IEEE Asia Pacific …, 2015 - ieeexplore.ieee.org
Tunnel FETs have attracted much attention recently for energy efficient designs. This paper
presents design, analysis and benchmarking of Tunnel FET (TFET) based reliable XOR …

High performance and energy efficient FinFET based 1-bit PT full adders

C Saraswathi, NU Rani… - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
This paper deals with the implementation of low voltage, energy efficient and high speed 1-
bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model …

Human action recognition by negative space analysis

SA Rahman, L Li, MKH Leung - 2010 International Conference …, 2010 - ieeexplore.ieee.org
We propose a novel region-based method to recognize human actions by analyzing regions
surrounding the human body, termed as negative space according to art theory, whereas …