Automated design for yield through defect tolerance

S Natarajan, AF Malavasi… - 2020 IEEE 38th VLSI …, 2020 - ieeexplore.ieee.org
We advocate defect tolerant design to improve timing yield. A metric of defect tolerance is
proposed, and an approach based on using defect tolerance metrics, derived for each cell in …

A defect tolerance framework for improving yield

SS Thiagarajan, S Natarajan, Y Makris - … of the 59th ACM/IEEE Design …, 2022 - dl.acm.org
In the latest technology nodes, there is a growing concern about yield loss due to timing
failures and delay degradation resulting from manufacturing complexities. Largely, these …

[PDF][PDF] Defect Tolerance Estimation and Netlist Optimization for Digital Designs

SS Thiagarajan, S Natarajan, Y Makris - utdallas.edu
Two important aspects of design-for-yield (DFY) are the design for functional yield and
parametric yield. While occurrences of gross defects leading to functional yield loss are fixed …