Advances in IC fabrication technology, coupled with aggressive circuit design, have led to
exponential growth of IC speed and integration levels. For these improvements to benefit …

The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …

This paper describes a dual delay-locked loop architecture which achieves low jitter,
unlimited (modulo 2/spl pi/) phase shift, and large operating range. The architecture employs …

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case
phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS …

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that
achieves both wide-range operation and low-jitter performance. A replica delay line is …

A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that
overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high …

We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps
operation over single-board and backplane FR4 channels with power efficiencies between …

A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for
example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper …

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel
applications. The module aligns the phase of a plesiochronous system clock to the incoming …

Synchronous CDMA/spread spectrum methods, devices, and systems are used to suppress
crosstalk in clock-forwarded on-chip interconnects. Transmitting a spread spectrum signal …