Study and analysis of advanced 3D multi-gate junctionless transistors
As the IC technology is evolving very rapidly, the feature size of the device has been
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
Analog/RF performance analysis of inner gate engineered junctionless Si nanotube
This paper investigates the analog/RF performance of inner gate engineered junctionless
silicon nanotube (JLSiNT) FETs. We demonstrate that the RF performance of symmetric …
silicon nanotube (JLSiNT) FETs. We demonstrate that the RF performance of symmetric …
Analysis and design of novel doping free silicon nanotube TFET with high-density meshing using ML for sub nanometre technology nodes
Beyond the 25 nm technological node, MOSFETs (metal oxide semiconductor FETs) have
worse channel electrostatic control than FinFETs (Fin field-effect transistors). It is necessary …
worse channel electrostatic control than FinFETs (Fin field-effect transistors). It is necessary …
Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective
This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
Study of 6T SRAM cell using high-k gate dielectric based junctionless silicon nanotube FET
This paper investigates the performance of 6 T SRAM cell using high-K gate dielectric based
junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate …
junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate …
Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance
This paper for the first time investigates the effect of temperature variation on analog/RF
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …
Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM
This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field‐
effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay …
effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay …
Single event performance of FED based SRAMs using numerical simulation
S PanneerSelvam, SK Pal, PV Chandramani… - Microelectronics …, 2023 - Elsevier
In this work, single event performance of field effect diode (FED) devices have been
investigated. Three variations of FED structures have been taken up for the study, and they …
investigated. Three variations of FED structures have been taken up for the study, and they …
Performance analysis of doping less nanotube tunnel field effect transistor for high speed applications
S Arun Jayakar, T Rajesh, NA Vignesh, S Kanithan - Silicon, 2022 - Springer
Abstract The DL-Si-NT-TFET (doping-free tunnelling Silicon Nanotube TFET) structure is
described in this article. In metals with adequate work functions, the Si-NT-TFET …
described in this article. In metals with adequate work functions, the Si-NT-TFET …
Structural Process Variation on Silicon Nanotube Tunnel Field-Effect Transistor
P Rajendiran, A Nisha Justeena - Silicon, 2023 - Springer
In this manuscript, we have investigated the geometrical process variation of a 3-dimensinal
silicon nanotube tunnel field effect transistor (Silicon NT-TFET) using TCAD numerical …
silicon nanotube tunnel field effect transistor (Silicon NT-TFET) using TCAD numerical …