[PDF][PDF] Abacus: All-bank activation counters for scalable and low overhead rowhammer mitigation
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …
technique that performance-, energy-, and area-efficiently scales with worsening …
{ABACuS}:{All-Bank} Activation Counters for Scalable and Low Overhead {RowHammer} Mitigation
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …
technique that performance-, energy-, and area-efficiently scales with worsening …
Memory access optimization of a neural network accelerator based on memory controller
R Wei, C Li, C Chen, G Sun, M He - Electronics, 2021 - mdpi.com
Special accelerator architecture has achieved great success in processor architecture, and it
is trending in computer architecture development. However, as the memory access pattern …
is trending in computer architecture development. However, as the memory access pattern …
A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems
TA Alawneh, AAM Sharadqh, A Alsharah… - IEEE …, 2024 - ieeexplore.ieee.org
Modern Dynamic Random Access Memory (DRAM) banks are characterized by their ability
to work in parallel, enabling concurrent servicing of multiple memory accesses through the …
to work in parallel, enabling concurrent servicing of multiple memory accesses through the …
Adaptive Image Size Padding for Load Balancing in System-on-Chip Memory Hierarchy
SY Kim, JY Hur - Electronics, 2023 - mdpi.com
The conventional address map often incurs traffic congestion in on-chip memory
components and degrades memory utilization when the access pattern of an application is …
components and degrades memory utilization when the access pattern of an application is …
Efficient generation of application specific memory controllers
The increasing gap between the bandwidth requirements of modern Systems on Chip (SoC)
and the I/O data rate delivered by Dynamic Random Access Memory (DRAM), known as the …
and the I/O data rate delivered by Dynamic Random Access Memory (DRAM), known as the …
Memory network architecture for packet processing in functions virtualization
T Korikawa, E Oki - IEEE Transactions on Network and Service …, 2022 - ieeexplore.ieee.org
Packet processing tasks in network functions require high-performance memory systems to
understand the packet information, update the packet content, and search the databases …
understand the packet information, update the packet content, and search the databases …
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping
The DRAM performance has become a critical bottleneck of modern computing systems.
Prior studies have proposed various optimization techniques on address mapping to bridge …
Prior studies have proposed various optimization techniques on address mapping to bridge …
CPR: Correlation-based Page Remapping
H Namkoong, J Kim - 2023 20th International SoC Design …, 2023 - ieeexplore.ieee.org
As the number of multimedia IPs in mobile devices increases, a high memory bandwidth
becomes essential. To meet this demand, Application Processors (APs) employ multiple …
becomes essential. To meet this demand, Application Processors (APs) employ multiple …
시스템온칩에서의부하균형을위한적응적주소매핑
김소연 - 2024 - oak.jejunu.ac.kr
시스템 온 칩에서 이차원 데이터를 처리할 때 기존의 주소 맵은 온칩 메모리 구성 요소에 트래픽
정체를 초래하는 경우가 있다. 또한 애플리케이션의 접근 패 턴이 주소 맵과 일치하지 않으면 …
정체를 초래하는 경우가 있다. 또한 애플리케이션의 접근 패 턴이 주소 맵과 일치하지 않으면 …