Safety-critical systems, formal methods and standards
J Bowen, V Stavridou - Software engineering journal, 1993 - IET
Standards concerned with the development of safety-critical systems, and the software in
such systems in particular, abound today as the software crisis increasingly affects the world …
such systems in particular, abound today as the software crisis increasingly affects the world …
Scalable trace signal selection using machine learning
A key problem in post-silicon validation is to identify a small set of traceable signals that are
effective for debug during silicon execution. Structural analysis used by traditional signal …
effective for debug during silicon execution. Structural analysis used by traditional signal …
Formal synthesis in circuit design—A classification and survey
R Kumar, C Blumenröhr, D Eisenbiegler… - Formal Methods in …, 1996 - Springer
This article gives a survey on different methods of formal synthesis. We define what we
mean by the term formal synthesis and delimit it from the other formal methods that can also …
mean by the term formal synthesis and delimit it from the other formal methods that can also …
Structuring and automating hardware proofs in a higher-order theorem-proving environment
R Kumar, K Schneider, T Kropf - Formal Methods in System Design, 1993 - Springer
In this article we present a structured approach to formal hardware verification by modeling
circuits at the register-transfer level using a restricted form of higher-order logic. This …
circuits at the register-transfer level using a restricted form of higher-order logic. This …
Combining model checking and theorem proving to verify parallel processes
H Hungar - … Aided Verification: 5th International Conference, CAV' …, 1993 - Springer
To overcome the limitations of pure model checking, this verification technique is combined
with theorem proving. Large processes are split into components whose correctness wrt …
with theorem proving. Large processes are split into components whose correctness wrt …
Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis
N Narasimhan, E Teica, R Radhakrishnan… - Formal Methods in …, 2001 - Springer
This paper presents a formal specification and a proof of correctness for the widely-used
Force-Directed List Scheduling (FDLS) algorithm for resource-constrained scheduling of …
Force-Directed List Scheduling (FDLS) algorithm for resource-constrained scheduling of …
Pops: mobile access to digital library resources
N Castellanos, JA Sánchez - 2003 Joint Conference on Digital …, 2003 - ieeexplore.ieee.org
Mobile devices not only represent new opportunities for accessing digital libraries (DLs) but
also pose a number of challenges given the diversity of their hardware and software …
also pose a number of challenges given the diversity of their hardware and software …
Performing high-level synthesis via program transformations within a theorem prover
C Blaumenrohr, D Eisenbiegler - … Conference (Cat. No …, 1998 - ieeexplore.ieee.org
In this paper, we present a new methodology towards performing high-level synthesis.
During high-level synthesis an algorithmic description is mapped to a structure of hardware …
During high-level synthesis an algorithmic description is mapped to a structure of hardware …
Formally embedding existing high level synthesis algorithms
D Eisenbiegler, R Kumar - … Conference on Correct Hardware Design and …, 1995 - Springer
This paper introduces a general scheme for formally embedding high level synthesis by
formulating its basic steps as transformations within higher order logic. A functional …
formulating its basic steps as transformations within higher order logic. A functional …
On the effectiveness of theorem proving guided discovery of formal assertions for a register allocator in a high-level synthesis system
N Narasimhan, R Vemuri - … Conference on Theorem Proving in Higher …, 1998 - Springer
This paper presents a formal specification and a proof of correctness for the register
optimization task in high-level synthesis. A widely implemented register optimization …
optimization task in high-level synthesis. A widely implemented register optimization …