Statistical static timing analysis: A survey

C Forzan, D Pandini - Integration, 2009 - Elsevier
As the device and interconnect physical dimensions decrease steadily in modern nanometer
silicon technologies, the ability to control the process and environmental variations is …

[图书][B] Statistical analysis and optimization for VLSI: Timing and power

A Srivastava, D Sylvester, D Blaauw - 2005 - Springer
Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …

Path sensitization in critical path problem (logic circuit design)

HC Chen, DHC Du - … on Computer-Aided Design of Integrated …, 1993 - ieeexplore.ieee.org
An important aspect of the critical path problem is deciding whether a path is sensitizable.
Three new path sensitization criteria are proposed in a general framework. Other path …

Delay fault models and coverage

AK Majhi, VD Agrawal - Proceedings Eleventh International …, 1998 - ieeexplore.ieee.org
Failures that cause logic circuits to malfunction at the desired clock rate and thus violate
timing specifications are currently receiving much attention. Such failures are modeled as …

[图书][B] Electrothermal analysis of VLSI systems

YK Cheng, CH Tsai, CC Teng, SMS Kang - 2005 - books.google.com
Electrothermal Analysis of VLSI Systems addresses electrothermal problems in modern
VLSI systems. Part I, The Building Blocks, discusses electrothermal phenomena and the …

pNovo+: de novo peptide sequencing using complementary HCD and ETD tandem mass spectra

H Chi, H Chen, K He, L Wu, B Yang… - Journal of proteome …, 2013 - ACS Publications
De novo peptide sequencing is the only tool for extracting peptide sequences directly from
tandem mass spectrometry (MS) data without any protein database. However, neither the …

[图书][B] Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and its Implications

PC McGeer, RK Brayton - 2012 - books.google.com
This book is an extension of one author's doctoral thesis on the false path problem. The work
was begun with the idea of systematizing the various solutions to the false path problem that …

A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs

Y Lee, T Kim - 16th Asia and South Pacific Design Automation …, 2011 - ieeexplore.ieee.org
As the technology scales, the increase of circuit delay over time due to NBTI (negative bias
temperature instability) effect is not negligible any more. It has been known that voltage …

Fast statistical timing analysis handling arbitrary delay correlations

M Orshansky, A Bandyopadhyay - … of the 41st Annual Design Automation …, 2004 - dl.acm.org
An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and
structural) causes of delay correlation is described. The algorithm derives the entire …

On the false path problem in hard real-time programs

P Altenbernd - Proceedings of the Eighth Euromicro Workshop …, 1996 - ieeexplore.ieee.org
The paper addresses the important subject of estimating the worst case execution time
(WCET) of hard real time programs essentially needed for further evaluation of real time …