A novel balanced ternary adder using recharged semi-floating gate devices

H Gundersen, Y Berg - … on Multiple-Valued Logic (ISMVL'06), 2006 - ieeexplore.ieee.org
This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with
Recharged Semi-Floating Gate Devices. By using balanced ternary notation, it possible to …

[PDF][PDF] Aspect of balanced ternary arithmetic implemented using CMOS recharged semi-floating gate device

H Gundersen - Oslo: Oslo University, 2008 - researchgate.net
Mostly all electronics used in computers today are based on binary logic. However, does the
binary logic have the capacity to be the leading technology in the future? Thus I raise the …

Delta-sigma ADC for ternary code system (Part I: Modulator realization)

AS Korotkov, DV Morozov, MM Pilipko… - … Symposium on Signals …, 2007 - ieeexplore.ieee.org
The paper presents realization of the delta-sigma modulator of analog-to-digital converter
(ADC) for ternary code signal processing. The modulator corresponds to the second order …

The design of ternary logic units on the basis of the standard MOS technology

DV Morozov, MM Pilipko, AS Korotkov - Russian Microelectronics, 2009 - Springer
Implementations of the basic ternary logic element and digital units with the use of the
balanced three-valued code are suggested. The logic states are supported by a bipolar …

Реализация устройств троичной логики на основе стандартной МОП технологии

ДВ Морозов, ММ Пилипко, АС Коротков - Микроэлектроника, 2009 - elibrary.ru
Предложены реализации базового логического элемента и цифровых устройств
троичной логики с использованием балансного троичного кода. Логические состояния …

Dual data-rate cyclic d/a converter using semi floating-gate devices

R Jensen, Y Berg - … on Multiple-Valued Logic (ISMVL'07), 2007 - ieeexplore.ieee.org
This paper focuses on compact and configurable multiple-valued (MV) encoders. For this
purpose, a new cyclic D/A converter circuit using semi floating-gate (SFG) inverters is …

Базовый троичный логический элемент на основе стандартной МОП технологии

АС Коротков, ДВ Морозов, ММ Пилипко - … перспективных микро-и …, 2008 - elibrary.ru
Предложена реализация базового логического элемента (вентиля) балансного
троичного кода. Логические состояния обеспечиваются за счет двуполярного источника …

Redundant Number Systems for Optimising Digital Signal Processing Performance in Field Programmable Gate Array

WHM Kamp - 2010 - ir.canterbury.ac.nz
Speeding up addition is the key to faster digital signal processing (DSP). This can be
achieved by exploiting the properties of redundant number systems. Their expanded symbol …

A novel ternary more, less and equality circuit using recharged semi-floating gate devices

H Gundersen, Y Berg - 2006 IEEE International Symposium on …, 2006 - ieeexplore.ieee.org
This paper presents a novel ternary more, less and equality (MLE) circuit implemented with
recharged semi-floating gate transistors. The circuit is a ternary application, and ternary …

[PDF][PDF] SYNTHESIS AND SIMULATION OF NOVEL MULTI VALUED LOGIC PROCESSOR ARCHITECTURE

SS NARKHEDE - 2016 - engg.matoshri.edu.in
SYNTHESIS AND SIMULATION OF NOVEL MULTI VALUED LOGIC PROCESSOR
ARCHITECTURE Page 1 SYNTHESIS AND SIMULATION OF NOVEL MULTI VALUED LOGIC …