Review of 3D networks-on-chip simulators and plugins

AAJ Al-Hchaimi, WN Flayyih, F Hashim… - 2021 IEEE Asia …, 2021 - ieeexplore.ieee.org
A comprehensive review focuses on 3D network-on-chip (NoC) simulators and plugins while
paying attention to the 2D simulators as the baseline is presented. Discussions include the …

Bandwidth-constrained multi-objective segmented brute-force algorithm for efficient mapping of embedded applications on NoC architecture

S Khan, S Anjum, UA Gulzari, T Umer, BS Kim - IEEE Access, 2017 - ieeexplore.ieee.org
Network-on-chip (NoC) is an emerging alternative to address the communication problem in
embedded system-on-chip designs. One of the key and major issues is the optimized …

An efficient algorithm for mapping real time embedded applications on NoC architecture

S Khan, S Anjum, UA Gulzari, MK Afzal, T Umer… - IEEE …, 2018 - ieeexplore.ieee.org
Network-on-chip (NoC) has appeared to be an impending substitute for the communication
paradigm in modern very large scale integration embedded systems. Apart from many …

Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks

UA Gulzari, Z Salcic, W Farooq, S Anjum, S Khan… - Computer Networks, 2024 - Elsevier
Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded
technologies. One of the main challenges of this system is its communication bottleneck …

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

AY Romanov, EV Lezhnev, AY Glukhikh… - Heliyon, 2020 - cell.com
This work is devoted to the study of application of new topologies in the design of networks-
on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC …

Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster

M Bertuletti, S Riedel, Y Zhang, A Vanelli-Coralli… - … on Embedded Computer …, 2023 - Springer
Synchronization is likely the most critical performance killer in shared-memory parallel
programs. With the rise of multi-core and many-core processors, the relative impact on …

Optical versus electrical: performance evaluation of network on-chip topologies for UWASN manycore processors

MR Yahya, N Wu, ZA Ali, Y Khizar - Wireless Personal Communications, 2021 - Springer
Optical network on chip (ONoC) has evolved as an innovative technology for on-chip
interconnects that can fulfill the upcoming requirements of manycore processors used in …

An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks

S Khan, S Anjum, UA Gulzari, F Ishmanov, M Palesi… - Applied …, 2018 - Springer
In this paper, we propose an optimized, search based near-optimal mapping heuristic,
named as ONMAP for mapping real time embedded application workloads on 2D based on …

NoC simulation steered by NEST: McAERsim and a Noxim patch

M Robens, R Kleijnen, M Schiek… - Frontiers in …, 2024 - frontiersin.org
Introduction Great knowledge was gained about the computational substrate of the brain, but
the way in which components and entities interact to perform information processing still …

SRNoC: An ultra-fast configurable FPGA-based NoC simulator using switch–router architecture

C Xu, Y Liu, Y Yang - … on Computer-Aided Design of Integrated …, 2019 - ieeexplore.ieee.org
Network-on-chip (NoC) has become one of the most common interconnection architectures
to integrate multicore system. However, the performance, hardware costs, and power …