A low-power high-speed comparator for precise applications
A Khorami, M Sharifkhani - IEEE Transactions on Very Large …, 2018 - ieeexplore.ieee.org
A low-power comparator is presented. pMOS transistors are used at the input of the
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …
Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems—A Review
K Aneesh, G Manoj, S Shylu Sam - Journal of Circuits, Systems and …, 2022 - World Scientific
In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators,
cochlear implants, visual prosthesis etc. have gained immense importance in the personal …
cochlear implants, visual prosthesis etc. have gained immense importance in the personal …
Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme
V Varshney, RK Nagaria - AEU-International Journal of Electronics and …, 2020 - Elsevier
In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass
transistors are used in the latch and pre-amplifier stage of the comparator. At the …
transistors are used in the latch and pre-amplifier stage of the comparator. At the …
A low-power dynamic comparator for low-offset applications
In this paper, a low-power method for double-tail comparators is introduced. Using the
proposed method, the power consumption of the pre-amplifier which is the dominant part is …
proposed method, the power consumption of the pre-amplifier which is the dominant part is …
A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique
A high-resolution dynamic voltage comparator with an input signal dependent power down
technique for low power applications is presented here. Without affecting the resolution, a …
technique for low power applications is presented here. Without affecting the resolution, a …
Design of dynamic comparator for low-power and high-speed applications
G Murali Krishna, G Karthick, N Umapathi - ICCCE 2020: Proceedings of …, 2020 - Springer
Most of the real world signals have analog behavior. In order to convert these analog signals
to digital, we need an analog to digital converter (ADC). In the architecture of ADC's …
to digital, we need an analog to digital converter (ADC). In the architecture of ADC's …
A low-power low-offset charge-sharing technique for double-tail comparators
A charge sharing technique for high-speed double-tail comparators is presented. This
technique is applied to the pre-amplifier stage of the dynamic comparators so that the …
technique is applied to the pre-amplifier stage of the dynamic comparators so that the …
[HTML][HTML] Design and analysis of optimized dynamic comparator circuit for low-power and high-speed applications
A typical dynamic comparator consists of two stages A first stage comprising a differential
amplifier and a second stage comprising latch-based circuitry. The primary function of the …
amplifier and a second stage comprising latch-based circuitry. The primary function of the …
An ultra low-power DAC with fixed output common mode voltage
A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive
Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC …
Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC …
Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications
ZM Moghadam, MR Salehi, SR Nashta… - Circuits, Systems, and …, 2024 - Springer
This paper presents an ultra-low power comparator with minimum delay and low offset, used
in successive approximation register analog-to-digital converters (SAR ADCs) for …
in successive approximation register analog-to-digital converters (SAR ADCs) for …