Memory bus encoding for low power: a tutorial

WC Cheng, M Pedram - Proceedings of the IEEE 2001. 2nd …, 2001 - ieeexplore.ieee.org
This paper contains a tutorial on bus-encoding techniques that target low power dissipation.
Three general classes of codes, ie, algebraic, permutation-based, and probability-based …

A subexponential algorithm for the discrete logarithm problem with applications to cryptography

L Adleman - 20th Annual Symposium on Foundations of Computer …, 1979 - computer.org
In this paper we describe a new method for encoding data streams on system buses in order
to reduce bus line transition activity. Our focus is on data streams whose statistical …

Methods and apparatus for constant-weight encoding & decoding

WP Cornelius, WC Athas - US Patent 6,661,355, 2003 - Google Patents
Methods and apparatus for spreading and concentrating information to constant-weight
encode data words on a parallel data line bus while allowing communication of information …

Method and apparatus for reducing delay in a bus provided from parallel, capacitively coupled transmission lines

PP Sotiriadis, A Chandrakasan - US Patent 7,400,276, 2008 - Google Patents
A mechanism for use with a bus provided from parallel, capacitively-coupled bus lines to
restrict a number of possible transitions on the bus to a number that is smaller than the …

Crosstalk avoidance and error-correction coding for coupled RLC interconnects

MS Rahaman, MH Chowdhury - 2009 IEEE International …, 2009 - ieeexplore.ieee.org
On-chip interconnect delay and crosstalk noise have become an important factor for
performance and signal integrity as a result of increase in device densities and operating …

[图书][B] Memory design techniques for low energy embedded systems

A Macii, L Benini, M Poncino - 2002 - books.google.com
The proliferation of embedded systems, and the corresponding new chip and chip set
designs, have brought additional attention to storage units. Indeed, the heterogeneity of …

Power protocol: reducing power dissipation on off-chip data buses

K Basu, A Choudhary, J Pisharath… - 35th Annual IEEE …, 2002 - ieeexplore.ieee.org
Power consumption is becoming increasingly important for both embedded and high-
performance systems. Off-chip data buses can be a major power consumer. In this paper we …

Why transition coding for power minimization of on-chip buses does not work

C Kretzschmar, AK Nieuwland… - … Design, Automation and …, 2004 - ieeexplore.ieee.org
Encoding techniques which minimize the self-or coupling activity of buses are often
proposed to reduce power dissipation on system buses. In this paper, we investigate the …

Power-optimal encoding for DRAM address bus

WC Cheng, M Pedram - … of the 2000 international symposium on Low …, 2000 - dl.acm.org
This paper presents Pyramid code, an optimal code for transmitting sequential addresses
over a DRAM bus. Constructed by finding an Eulerian cycle on a complete graph, this code …

Low-energy for deep-submicron address buses

L Macchiarulo, E Macii, M Poncino - Proceedings of the 2001 …, 2001 - dl.acm.org
In this paper, we introduce a new encoding scheme that explicitly targets the minimization of
the bus energy due to the crosstalk capacitances between adjacent bus lines. The key …