Multi-layer memory resiliency
With memories continuing to dominate the area, power, cost and performance of a design,
there is a critical need to provision reliable, high-performance memory bandwidth for …
there is a critical need to provision reliable, high-performance memory bandwidth for …
Coupling mitigation in 3-D multiple-stacked devices
A 3-D multiple-stacked IC has been proposed to support energy efficiency for data center
operations as dynamic RAM (DRAM) scaling improves annually. 3-D multiple-stacked IC is a …
operations as dynamic RAM (DRAM) scaling improves annually. 3-D multiple-stacked IC is a …
Locality transformations and prediction techniques for optimizing multicore memory performance
AHA Badawy - 2013 - search.proquest.com
Abstract Chip Multiprocessors (CMPs) are here to stay for the foreseeable future. In terms of
programmability of these processors what is different from legacy multiprocessors is that …
programmability of these processors what is different from legacy multiprocessors is that …
Reliable and Real-Time Distributed Abstractions
D Kozhaya - 2016 - infoscience.epfl.ch
The celebrated distributed computing approach for building systems and services using
multiple machines continues to expand to new domains. Computation devices nowadays …
multiple machines continues to expand to new domains. Computation devices nowadays …
[图书][B] Resilient On-Chip Memory Design in the Nano Era
A BanaiyanMofrad - 2015 - search.proquest.com
Aggressive technology scaling in the nano-scale regime makes chips more susceptible to
failures. This causes multiple reliability challenges in the design of modern chips, including …
failures. This causes multiple reliability challenges in the design of modern chips, including …