Symbolic boolean manipulation with ordered binary-decision diagrams

RE Bryant - ACM Computing Surveys (CSUR), 1992 - dl.acm.org
Ordered Binary-Decision Diagrams (OBDDs) represent Boolean functions as directed
acyclic graphs. They form a canonical representation, making testing of functional properties …

Verification techniques for cache coherence protocols

F Pong, M Dubois - ACM Computing Surveys (CSUR), 1997 - dl.acm.org
In this article we present a comprehensive survey of various approaches for the verification
of cache coherence protocols based on state enumeration,(symbolic model checking, and …

Bounded model checking using satisfiability solving

E Clarke, A Biere, R Raimi, Y Zhu - Formal methods in system design, 2001 - Springer
The phrase model checking refers to algorithms for exploring the state space of a transition
system to determine if it obeys a specification of its intended behavior. These algorithms can …

Model checking and modular verification

O Grumberg, DE Long - ACM Transactions on Programming Languages …, 1994 - dl.acm.org
We describe a framework for compositional verification of finite-state processes. The
framework is based on two ideas: a subset of the logic CTL for which satisfaction is …

Symbolic model checking for sequential circuit verification

JR Burch, EM Clarke, DE Long… - IEEE Transactions on …, 1994 - ieeexplore.ieee.org
The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is
modified to represent state graphs using binary decision diagrams (BDD's) and partitioned …

[图书][B] Symbolic model checking with partitioned transition relations

JR Burch, EM Clarke, DE Long - 1991 - Citeseer
We signi cantly reduce the complexity of BDD-based symbolic veri cation by using
partitioned transition relations to represent state transition graphs. This method can be …

The birth of model checking

EM Clarke - 25 Years of model checking: history, achievements …, 2008 - Springer
The Birth of Model Checking* Page 1 The Birth of Model Checking* Edmund M. Clarke
Department of Computer Science Carnegie Mellon University Pittsburgh, PA, USA emc@cs.cmu.edu …

[PDF][PDF] Programming and verifying real-time systems by means of the synchronous data-flow language LUSTRE

N Halbwachs, F Lagnier… - IEEE transactions on …, 1992 - homepage.divms.uiowa.edu
We investigate the bene ts of using a synchronous data-ow language for programming
critical real-time systems. These bene ts concern ergonomy| since the data ow approach …

[图书][B] Real-time systems: scheduling, analysis, and verification

AMK Cheng - 2003 - books.google.com
Test und Validierung spielen bei Echtzeitsystemen eine zentrale Rolle: Auf die
Spezifikationen, die der Hersteller angibt, muss sich der Kunde hier in besonders hohem …

Formal hardware verification methods: A survey

A Gupta - Formal Methods in System Design, 1992 - Springer
Growing advances in VLSI technology have led to an increased level of complexity in
current hardware systems. Late detection of design errors typically results in higher costs …