This paper presents the design and the analysis of power efficient binary content
addressable memory (PEBCAM) core cells using the energy recovery principle of adiabatic …

With continuous advancements evolving in the VLSI design arena, the real time chips which
operates on the principle of charge recovery logic realizes substantially lower power …

This paper presents FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL)
powered by four-phase power clock capable of operating up to 1 GHz with low energy …

A novel, energy efficient and power analysis robust logic style called the charge balancing
symmetric pre‐resolve adiabatic logic (CBSPAL) is proposed to overcome the susceptibility …

This paper presents the quasi-adiabatic logic for low power powered by two phase
sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic …

The recent trends in the developments and advancements in the area of low power VLSI
Design are surveyed in this paper. Though Low Power is a well established domain, it has …

In recent years, side channel attacks such as Differential Power Analysis (DPA) and Simple
Power Analysis (SPA) are the most common in cryptographic hardware systems. Smart …

Hardware security modules have become quintessential as the digital systems continue
evolving. Physical Unclonable Function (PUF) is a hardware security module that exploits …

Binary multiplier is one of the most time and power consuming architectures in an ALU. The
performance efficiency of complex computations is determined by the multiplier algorithm …

Abstract FinFET based Improved Pass-transistor Adiabatic Logic (IPAL) powered by four-
phase power-clock is presented. Capable of operating across MHz to GHz frequency range …