Temperature-aware resource allocation and binding in high-level synthesis

R Mukherjee, SO Memik, G Memik - Proceedings of the 42nd annual …, 2005 - dl.acm.org
Physical phenomena such as temperature have an increasingly important role in
performance and reliability of modern process technologies. This trend will only strengthen …

A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of …

DS Harish Ram, MC Bhuvaneswari, SS Prabhu - VLSI design, 2012 - Wiley Online Library
High‐Level Synthesis deals with the translation of algorithmic descriptions into an RTL
implementation. It is highly multi‐objective in nature, necessitating trade‐offs between …

High-level synthesis for low-power design

Z Zhang, D Chen, S Dai, K Campbell - IPSJ Transactions on System …, 2015 - jstage.jst.go.jp
Power and energy efficiency have emerged as first-order design constraints across the
computing spectrum from handheld devices to warehouse-sized datacenters. As the number …

Simultaneous FU and register binding based on network flow method

J Cong, J Xu - Proceedings of the conference on Design, automation …, 2008 - dl.acm.org
With the rapid increase of design complexity and the decrease of device features in nano-
scale technologies, interconnection optimization in digital systems becomes more and more …

A novel evolutionary technique for multi-objective power, area and delay optimization in high level synthesis of datapaths

DSH Ram, MC Bhuvaneswari… - 2011 IEEE Computer …, 2011 - ieeexplore.ieee.org
The use of multi-objective approaches in High Level Synthesis has been gaining lot of
interest in recent years since the major design objectives such as area, delay and power are …

Variability-driven module selection with joint design time optimization and post-silicon tuning

F Wang, X Wu, Y Xie - 2008 Asia and South Pacific Design …, 2008 - ieeexplore.ieee.org
Increasing delay and power variation are significant challenges to the designers as
technology scales to the deep sub-micron (DSM) regime. Traditional module selection …

Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

N Chabini, W Wolf - IEEE transactions on very large scale …, 2005 - ieeexplore.ieee.org
Scheduling and binding are two tasks found in high-level synthesis of hardware as well as in
compiling software. These tasks are realized on graphs that are models of the hardware or …

Optimal module and voltage assignment for low-power

D Chen, J Cong, J Xu - Proceedings of the 2005 Asia and South Pacific …, 2005 - dl.acm.org
Reducing power consumption through high-level synthesis has attracted a growing interest
from researchers due to its large potential for power reduction. In this work we study …

Optimality study of resource binding with multi-Vdds

D Chen, J Cong, Y Fan, J Xu - Proceedings of the 43rd annual Design …, 2006 - dl.acm.org
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to
reduce dynamic power consumption. In this work we present an optimality study for resource …

Optimal simultaneous module and multivoltage assignment for low power

D Chen, J Cong, J Xu - ACM Transactions on Design Automation of …, 2006 - dl.acm.org
Reducing power consumption through high-level synthesis has attracted a growing interest
from researchers due to its large potential for power reduction. In this work we study …