Transaction-level model simulator for communication-limited accelerators

S Kim, J Wang, Y Seo, S Lee, Y Park, S Park… - arXiv preprint arXiv …, 2020 - arxiv.org
Rapid design space exploration in early design stage is critical to algorithm-architecture co-
design for accelerators. In this work, a pre-RTL cycle-accurate accelerator simulator based …

Dynamic data allocation and task scheduling on multiprocessor systems with NVM-based SPM

Y Wang, K Li, K Li - IEEE Access, 2018 - ieeexplore.ieee.org
Low-power and short-latency memory access is critical to the performance of chip
multiprocessor (CMP) system devices, especially to bridge the performance gap between …

[图书][B] Dynamic memory management for embedded systems

DA Alonso, S Mamagkakis, C Poucet, M Peón-Quirós… - 2015 - Springer
Modern embedded systems in mobile and multimedia applications offer a wide range of
features. They can also communicate to different devices using different standards which …

Improving dynamic memory allocation on many-core embedded systems with distributed shared memory

I Koutras, I Anagnostopoulos, A Bartzas… - IEEE Embedded …, 2016 - ieeexplore.ieee.org
Memory management on many-core architectures is a major challenge for improving the
overall system performance. Memory resources are distributed over nodes for faster local …

Energy efficiency effects of vectorization in data reuse transformations for many-core processors—a case study

A Al Hasib, L Natvig, PG Kjeldsberg… - Journal of Low Power …, 2017 - mdpi.com
Thread-level and data-level parallel architectures have become the design of choice in
many of today's energy-efficient computing systems. However, these architectures put …

Data‐aware task scheduling on heterogeneous hybrid memory multiprocessor systems

J Chen, K Li, Z Tang, C Liu, Y Wang… - … Practice and Experience, 2016 - Wiley Online Library
In this paper, we propose a method about task scheduling and data assignment on
heterogeneous hybrid memory multiprocessor systems for real‐time applications. In a …

Performance and energy efficiency analysis of data reuse transformation methodology on multicore processor

AA Hasib, PG Kjeldsberg, L Natvig - … Islands, Greece, August 27-31, 2012 …, 2013 - Springer
Memory latency and energy efficiency are two key constraints to high performance
computing systems. Data reuse transformations aim at reducing memory latency by …

Dynamic voltage and frequency scaling and adaptive body biasing for active and leakage power reduction in MPSoC: A literature overview

A Milutinovic, A Molnos, K Goossens… - 20th Annual Workshop …, 2009 - research.utwente.nl
Power is an important design constraint for all nomadic and tethered devices as mobile
phones or media-boxes today. This is mainly because it limits their operational time or …

Optimisation de l'énergie dans une architecture mémoire multi-bancs pour des applications multi-tâches temps réel

HB Fradj - 2006 - theses.hal.science
De nombreuses techniques ont été développées pour réduire la consommation processeur
considéré jusqu'à présent comme l'élément le plus gourmand en consommation. Avec …

Placement of linked dynamic data structures over heterogeneous memories in embedded systems

M Peon-Quiros, A Bartzas, S Mamagkakis… - ACM Transactions on …, 2015 - dl.acm.org
Software applications use dynamic memory (allocated and deallocated in the system's
heap) to handle dynamism in their working conditions. Embedded systems tend to include …