[PDF][PDF] Glicbawls-Grey Level Image Compression by Adaptive Weighted Least Squares.
B Meyer, PE Tischer - Data Compression Conference, 2001 - researchgate.net
In recent years, most research into lossless and near-lossless compression of greyscale
images could be characterized as belonging to either of two distinct groups. The first group …
images could be characterized as belonging to either of two distinct groups. The first group …
Low voltage and low power divide-by-2/3 counter design using pass transistor logic circuit technique
An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low
supply voltage and low power consumption applications is presented. By using a wired or …
supply voltage and low power consumption applications is presented. By using a wired or …
A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment
Z Tibenszky, M Kreißig, C Carta… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This research work presents the analysis, design, and characterization of a concept for an
mm-wave divide-by-4 frequency divider utilizing an extended true single-phase clock (E …
mm-wave divide-by-4 frequency divider utilizing an extended true single-phase clock (E …
A high speed counter for analog-to-digital converters
PR Thota, AK Mal - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
A high speed and power efficient synchronous counter is proposed using True Single-Phase
Clock (TSPC) based Toggle Flip-Flop (TFF) with the Extended True Single-Phase Clock (E …
Clock (TSPC) based Toggle Flip-Flop (TFF) with the Extended True Single-Phase Clock (E …
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 ͘m CMOS technology
FPH de Miranda, J Navarro S Jr… - Proceedings of the 17th …, 2004 - dl.acm.org
The design of a dual modulus prescaler 32/33 in a 0.35 μm CMOS technology is presented.
The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed …
The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed …
Low-power programmable divider with a shared counter for frequency synthesiser
KY Kim, YJ Min, SW Kim, J Park - IET circuits, devices & systems, 2011 - IET
A low-power programmable divider (PD) for frequency synthesiser is presented in this study.
Instead of two counters used in conventional PD, a shared counter with a small control …
Instead of two counters used in conventional PD, a shared counter with a small control …
Low-power programmable divider for multi-standard frequency synthesizers using reset and modulus signal generator
KY Kim, WK Lee, H Kim, SW Kim - 2008 IEEE Asian Solid-State …, 2008 - ieeexplore.ieee.org
This paper proposes a low-power programmable divider for multi-standard frequency
synthesizers using a reset and modulus control signal (RMS) generator. The use of RMS …
synthesizers using a reset and modulus control signal (RMS) generator. The use of RMS …
Dynamic floating input D flip-flop
TS Jau, WB Yang, YL Lo - US Patent 7,656,211, 2010 - Google Patents
(57) ABSTRACT A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF
includes a floating input stage, a first string of transistors, and a second string of transistors …
includes a floating input stage, a first string of transistors, and a second string of transistors …
Design of high speed digital circuits with E-TSPC cell library
The application of a standard cells library with Extended True Single Phase Clock (E-TSPC)
blocks in the design of high speed digital circuits is analyzed. The E-TSPC technique has …
blocks in the design of high speed digital circuits is analyzed. The E-TSPC technique has …
A new dynamic floating input D flip-flop (DFIDFF) for high speed and ultra low voltage divided-by 4/5 prescaler
TS Jau, WB Yang, YL Lo - 2006 13th IEEE International …, 2006 - ieeexplore.ieee.org
A new ultra low voltage dynamic floating input D flip-flop (DFIDFF) is proposed for high
speed prescaler circuit. Prescaler and VCO are the main blocks that determining the speed …
speed prescaler circuit. Prescaler and VCO are the main blocks that determining the speed …