IBM POWER9 circuit design and energy optimization for 14-nm technology
EJ Fluhr, RM Rao, H Smith… - IBM Journal of …, 2018 - ieeexplore.ieee.org
Modern multicore microprocessors require attentive development to energy requirements
when maximizing power-performance efficiency and ensuring reliable plus scalable …
when maximizing power-performance efficiency and ensuring reliable plus scalable …
Heterogeneity aware power abstractions for dynamic power dominated FinFET‐based microprocessors
S Rachamalla, S Reddy… - IET Computers & Digital …, 2019 - Wiley Online Library
In dynamic power dominated FinFET‐based microprocessors, there is significant
heterogeneity in the chip power profile induced due to various factors. The workloads the …
heterogeneity in the chip power profile induced due to various factors. The workloads the …
[PDF][PDF] IBM POWER9 circuit design and energy optimization for 14-nm technology
R Bertran - researchgate.net
The IBM POWER9 microprocessor family [1] comprises up to 12 SMT8 or 24 SMT4
processor cores, 6 MB of Level 2 (L2), and 120 MB of Level 3 (L3) cache per chip. A “nest” …
processor cores, 6 MB of Level 2 (L2), and 120 MB of Level 3 (L3) cache per chip. A “nest” …