Acoustic-sensor-based soft error resilience is particularly promising, since it can verify the
absence of soft errors and eliminate silent data corruptions at a low hardware cost. However …

Superscalar out-of-order cores deliver high performance at the cost of increased complexity
and power budget. In-order cores, in contrast, are less complex and have a smaller power …

Out-of-order superscalar processors are currently the only architecture that speeds up
irregular programs, but they suffer from poor power efficiency. To tackle this issue, we …

Out-of-order cores provide high performance at the cost of energy efficiency. Dynamic
scheduling is one of the major contributors to this: generating highly optimized issue …

Issue time prediction processors use dataflow dependencies and predefined instruction
latencies to predict issue times of repeated instructions. In this work, we make two key …

Modern out-of-order processors call for more aggressive scheduling techniques such as
priority scheduling and out-of-order commit to make use of increasing core resources. Since …

Reliability against errors, such as soft errors—transient bit flips in transistors caused by
energetic particle strikes—and crash inconsistency arising from power failure, is as crucial …

Superscalar out-of-order cores deliver high performance at the cost of increased complexity
and power budget. In-order cores, in contrast, are less complex and have a smaller power …

The rise of RISC-V Instruction Set Architecture (ISA) motivates research on improving the
performance of the RISC-V processors. Issue Queue (IQ) is an essential factor affecting the …

Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level
cache access latencies. While out-of-order (OoO) cores, and techniques building on them …