[图书][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
Expression of Concern: On the Optimal Design, Performance, and Reliability of Future Carbon Nanotube-Based Interconnect Solutions
A Nieuwoudt, Y Massoud - IEEE transactions on electron …, 2008 - ieeexplore.ieee.org
In this paper, we develop comprehensive modeling and design techniques for carbon
nanotube (CNT)-based interconnects, which we utilize to examine the performance …
nanotube (CNT)-based interconnects, which we utilize to examine the performance …
A resistive TCAM accelerator for data-intensive computing
Power dissipation and off-chip bandwidth restrictions are critical challenges that limit
microprocessor performance. Ternary content addressable memories (TCAM) hold the …
microprocessor performance. Ternary content addressable memories (TCAM) hold the …
[图书][B] Design for manufacturability and yield for nano-scale CMOS
C Chiang, J Kawa - 2007 - books.google.com
Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all
the aspects of manufacturability and yield in a nano-CMOS process and how to address …
the aspects of manufacturability and yield in a nano-CMOS process and how to address …
[图书][B] Introduction to VLSI systems: a logic, circuit, and system perspective
MB Lin - 2011 - taylorfrancis.com
With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip
(SoC) has become an essential technique to reduce product cost. With this progress and …
(SoC) has become an essential technique to reduce product cost. With this progress and …
Global and detailed routing
HY Chen, YW Chang - Electronic Design Automation, 2009 - Elsevier
Publisher Summary This chapter focuses on routing, a process that determines the precise
paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the …
paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the …
A novel wire-density-driven full-chip routing system for CMP variation control
HY Chen, SJ Chou, SL Wang… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
As nanometer technology advances, the post chemical-mechanical polishing (CMP)
topography variation control becomes crucial for manufacturing closure. To improve the …
topography variation control becomes crucial for manufacturing closure. To improve the …
Model based layout pattern dependent metal filling algorithm for improved chip surface uniformity in the copper process
Thickness range, ie the difference between the highest point and the lowest point of the chip
surface, is a key indicator of chip yield. This paper presents a novel metal filling algorithm …
surface, is a key indicator of chip yield. This paper presents a novel metal filling algorithm …
Crosstalk-induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technology
A Nieuwoudt, J Kawa… - IEEE transactions on very …, 2009 - ieeexplore.ieee.org
In this paper, we investigate the crosstalk-induced delay, noise, and chemical mechanical
polishing (CMP)-induced thickness-variation implications of dummy fill generated using rule …
polishing (CMP)-induced thickness-variation implications of dummy fill generated using rule …
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment
Dummy filling is widely applied to significantly improve the planarity of topographic patterns
for the chemical mechanical polishing (CMP) process in VLSI manufacturing. In the dummy …
for the chemical mechanical polishing (CMP) process in VLSI manufacturing. In the dummy …