Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

This chapter reviews two basic sets of netweighting algorithms: static netweighting and
dynamic netweighting. It explores two global placement approaches: partitioning and force …

In this paper, we propose a new timing-driven detailed placement technique for FPGAs
based on optimizing critical paths. Our approach extends well beyond the previously known …

Physical synthesis optimizations and engineering change orders typically change the
locations of cells, resize cells or add more cells to the design after global placement …

We have developed a design flow from Verilog/VHDL to layout that mitigates the timing
closure problem, while requiring no timing driven placement or routing tools. Timing issues …

Advanced technologies are expected to reduce interconnect delays and increase transistor
packing densities to allow for the continuation of Moore's Law. These advancements are …

We have developed a complete design flow from Verilog/VHDL to layout that generates
what is effectively a post-layout power versus delay curve for a digital IC block. Post-layout …

In deep sub-micron technology nodes, Application-Specific Integrated Circuits (ASICs) are
becoming expensive to design and manufacture. For this reason, Field Programmable Gate …

Embedded hard real-time systems have stringent timing constraints that must be satisfied for
the correct functioning of the system. Additionally, there are systems where energy is …

The main purpose of VLSI placement is to place the objects into fixed chip such that there
should be no overlaps among the objects and some cost metric such as wire length and …