Reducing datacenter compute carbon footprint by harnessing the power of specialization: Principles, metrics, challenges and opportunities
Computing is an indispensable tool in addressing climate change, but it also contributes to a
significant and steadily increasing carbon footprint, partly due to the exponential growth in …
significant and steadily increasing carbon footprint, partly due to the exponential growth in …
BlitzCoin: Fully Decentralized hardware power management for accelerator-rich SoCs
On-chip power-management techniques have evolved over several processor generations.
However, response time and scalability constraints have made it difficult to translate existing …
However, response time and scalability constraints have made it difficult to translate existing …
FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support
The new generation of domain-specific AI accelerators is characterized by rapidly increasing
demands for bulk data transfers, as opposed to small, latency-critical cache line transfers …
demands for bulk data transfers, as opposed to small, latency-critical cache line transfers …
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory
Resource-constrained system-on-chips (SoCs) are increasingly heterogeneous with
specialized accelerators for various tasks. Acceleration taxes due to control and data …
specialized accelerators for various tasks. Acceleration taxes due to control and data …
Transforming the Hybrid Cloud for Emerging AI Workloads
This white paper, developed through close collaboration between IBM Research and UIUC
researchers within the IIDAI Institute, envisions transforming hybrid cloud systems to meet …
researchers within the IIDAI Institute, envisions transforming hybrid cloud systems to meet …
Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators
R Wang, B Yan - arXiv preprint arXiv:2411.13054, 2024 - arxiv.org
Processing-in-memory (PIM) is a promising choice for accelerating deep neural networks
(DNNs) featuring high efficiency and low power. However, the rapid upscaling of neural …
(DNNs) featuring high efficiency and low power. However, the rapid upscaling of neural …
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures
J Zuckerman, JD Wellman, A Vanamali… - arXiv preprint arXiv …, 2024 - arxiv.org
We present several enhancements to the open-source ESP platform to support flexible and
efficient on-chip communication for programmable accelerators in heterogeneous SoCs …
efficient on-chip communication for programmable accelerators in heterogeneous SoCs …