Microelectronic elements having metallic pads overlying vias

V Oganesian, I Mohammed, C Mitchell, B Haba… - US Patent …, 2014 - Google Patents
(56) References Cited 2004/0043607 A1 3/2004 Farnworth et al. 2004/0051173 A1 3, 2004
Koh et al. US PATENT DOCUMENTS 2004/006 1238 A1 4/2004 Sekine 2004/0104454 A1 …

Microelectronic elements with rear contacts connected with via first or via middle structures

V Oganesian, B Haba, I Mohammed, C Mitchell… - US Patent …, 2014 - Google Patents
(57) ABSTRACT A microelectronic unit includes a microelectronic element, eg, an integrated
circuit chip, having a semiconductor region of monocrystalline form. The semiconductor …

Integrated circuits protected by substrates with cavities, and methods of manufacture

H Shen, CG Woychik, AR Sitaram - US Patent 10,446,456, 2019 - Google Patents
Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an
interposer, and are protected by a protective substrate (410) attached to a wiring substrate …

Chips having rear contacts connected by through vias to front contacts

B Haba, KA Honer, DB Tuckerman… - US Patent …, 2013 - Google Patents
US8405196B2 - Chips having rear contacts connected by through vias to front contacts -
Google Patents US8405196B2 - Chips having rear contacts connected by through vias to …

Integrated circuit assemblies with reinforcement frames, and methods of manufacture

R Katkar, LW Mirkarimi, A Sitaram… - US Patent …, 2016 - Google Patents
(51) Int. Cl. 6,746,876 B2 6/2004 Itoh et al. 6,787,916 B2 9/2004 Halahan HOIL
2L/66(2006.01) 6,947,275 B1 9, 2005 Anderson et al. HOIL 2L/78(2006.01) 6,958,285 B2 …

Making electrical components in handle wafers of integrated circuit packages

L Wang, H Shen, R Katkar - US Patent 9,165,793, 2015 - Google Patents
US PATENT DOCUMENTS tribution layer (RDL) of the interposer. The lower surface of the
handle wafer is bonded to the upper surface of the inter poser such that the die is disposed …

Vias in porous substrates

I Mohammed, B Haba, CE Uzoh, P Savalia - US Patent 9,455,181, 2016 - Google Patents
A microelectronic unit can include a substrate having front and rear surfaces and active
semiconductor devices therein, the substrate having a plurality of openings arranged in a …

Single layer low cost wafer level packaging for SFF SiP

C Hu, V Nair - US Patent 9,281,292, 2016 - Google Patents
In one embodiment of the invention, a system in package (SiP) is described which includes
a plurality of device components with different form factors embedded within a molding …

Multi-chip module with stacked face-down connected dies

B Haba, I Mohammed, P Savalia - US Patent 8,841,765, 2014 - Google Patents
(57) ABSTRACT A microelectronic assembly can include a Substrate having first and
second Surfaces, at least two logic chips overlying the first surface, and a memory chip …

Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication

H Shen, L Wang, R Katkar - US Patent 9,324,626, 2016 - Google Patents
US9324626B2 - Interposers with circuit modules encapsulated by moldable material in a cavity,
and methods of fabrication - Google Patents US9324626B2 - Interposers with circuit modules …