A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs
D Turker, A Bekele, P Upadhyaya… - … Solid-State Circuits …, 2018 - ieeexplore.ieee.org
Direct-RF data converters [1, 2] have seen increased adoption in remote-radio-head TX and
RX, due to their unparalleled bandwidth and flexibility. However, since these converters …
RX, due to their unparalleled bandwidth and flexibility. However, since these converters …
A Type-I Sub-Sampling PLL With a Footprint and −255-dB FOM
A Sharkia, S Mirabbasi… - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
A dual-loop LC-voltage-controlled oscillator (VCO) based frequency synthesizer, composed
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
A 14-GHz bang-bang digital PLL with sub-150-fs integrated jitter for wireline applications in 7-nm FinFET CMOS
D Pfaff, R Abbott, XJ Wang, S Moazzeni… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
Demands for increased wireline data throughput necessitate multi-gigahertz clock sources
of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked …
of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked …
A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction
This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a
novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …
novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …
A 2.2-GHz 3.2-mW DTC-Free Sampling Fractional- PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur
This paper presents the first sampling ΔΣ fractional-N phase-locked loop (PLL) without a
digital-to-time converter (DTC), whose design is challenging and requires complex …
digital-to-time converter (DTC), whose design is challenging and requires complex …
A 0.008mm2 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a −239.7dB FoM and −64dBc reference spurs
A ring-oscillator (RO) based PLL is presented combining a type-I architecture and a sub-
sampling phase detector (SSPD). It achieves low jitter thanks to the wide-bandwidth type-I …
sampling phase detector (SSPD). It achieves low jitter thanks to the wide-bandwidth type-I …