Noise and Defects in Microelectronic Materials and Devices
DM Fleetwood - IEEE Transactions on Nuclear Science, 2015 - ieeexplore.ieee.org
This paper reviews and compares predictions of the Dutta-Horn model of low-frequency
excess (1/f) noise with experimental results for thin metal films, MOS transistors, and …
excess (1/f) noise with experimental results for thin metal films, MOS transistors, and …
Ionizing radiation damage in 65 nm CMOS technology: Influence of geometry, bias and temperature at ultra-high doses
G Borghello, E Lerario, F Faccio, HD Koch… - Microelectronics …, 2021 - Elsevier
We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-
high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of …
high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of …
65 nm CMOS analog front-end for pixel detectors at the HL-LHC
This work is concerned with the design and the experimental characterization of analog front-
end electronics conceived for experiments with unprecedented particle rates and radiation …
end electronics conceived for experiments with unprecedented particle rates and radiation …
Assessment of a low-power 65 nm CMOS technology for analog front-end design
This work is concerned with the study of the analog properties of MOSFET devices
belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise …
belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise …
Ionizing radiation effects on the noise of 65 nm CMOS transistors for pixel sensor readout at extreme total dose levels
This paper is focused on the study of the noise performance of 65 nm CMOS transistors at
extremely high total ionizing dose (TID) levels of the order of several hundreds of Mrad (SiO …
extremely high total ionizing dose (TID) levels of the order of several hundreds of Mrad (SiO …
Perspectives of 65 nm CMOS technologies for high performance front-end electronics
The 65 nm CMOS generation is currently being evaluated as a promising solution for the
integration of high speed circuits with high functional density in a small pixel. This …
integration of high speed circuits with high functional density in a small pixel. This …
Radiation tolerance of devices and circuits in a 3D technology based on the vertical integration of two 130-nm CMOS layers
Total ionizing dose effects are studied in 130-nm transistors and pixel sensors in a vertically
integrated two-layer CMOS technology, evaluating the possible impact of 3D integration on …
integrated two-layer CMOS technology, evaluating the possible impact of 3D integration on …
Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications
This work is concerned with the design and characterization of bandgap reference circuits
capable of operating with a power supply of 1.2 V in view of applications to HL-LHC …
capable of operating with a power supply of 1.2 V in view of applications to HL-LHC …
A 65 nm CMOS analog processor with zero dead time for future pixel detectors
L Gaioni, D Braga, DC Christian, G Deptuch… - Nuclear Instruments and …, 2017 - Elsevier
Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely
high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and …
high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and …
TID-induced degradation in static and noise behavior of sub-100 nm multifinger bulk NMOSFETs
This paper is concerned with the study of the total ionizing dose (TID) effects in NMOS
transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers …
transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers …