Near-Threshold Wide-Voltage Design Review

Y Zhao, J Yang, C Chen, W Shan, P Cao… - Tsinghua Science …, 2023 - ieeexplore.ieee.org
This paper presents a comprehensive review of near-threshold wide-voltage designs on
memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing …

[HTML][HTML] Analysis of the subthreshold CMOS logic inverter

SM Sharroush - Ain Shams Engineering Journal, 2018 - Elsevier
There is no doubt that operating the MOSFET transistor in the subthreshold region, where
the power-supply voltage is less than the threshold voltage, has an increasing importance …

An analytical gate delay model in near/subthreshold domain considering process variation

P Cao, Z Liu, J Guo, J Wu - IEEE Access, 2019 - ieeexplore.ieee.org
Voltage scaling technique is widely employed in state-of-the-art low power circuits with
excellent power reduction. However, voltage scaling to sub-threshold (STV) and near …

Variation-resilient building blocks for ultra-low-energy sub-threshold design

N Reynders, W Dehaene - … on Circuits and Systems II: Express …, 2012 - ieeexplore.ieee.org
This paper presents the design of variation-resilient ultra-low-voltage circuits functioning at
MHz-speed. By careful design, robust digital circuits operating in the sub-threshold region …

A Statistical Cell Delay Model for Estimating the 3σ Delay by Matching Kurtosis

L Jin, W Fu, H Yan, L Shi - … on Circuits and Systems II: Express …, 2022 - ieeexplore.ieee.org
Accurate standard cell modeling is significant for circuit timing analysis and yield estimation.
With voltage decreasing to near-threshold, cell delay distribution becomes asymmetrical and …

Energy optimized subthreshold VLSI logic family with unbalanced pull-up/down network and inverse narrow-width techniques

MZ Li, CI Ieong, MK Law, PI Mak, MI Vai… - … Transactions on Very …, 2015 - ieeexplore.ieee.org
Ultralow-energy biomedical applications have urged the development of a subthreshold
VLSI logic family in standard CMOS. This brief proposes an unbalanced pull-up/down …

All-region statistical model for delay variation based on log-skew-normal distribution

HA Balef, M Kamal, A Afzali-Kusha… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
In this paper, we propose a single probability density function for the distributions of the
delay in the presence of the process variation for different regions of operation. The delay …

Offset-calibration with time-domain comparators using inversion-mode varactors

R Fiorelli, M Delgado-Restituto… - … on Circuits and …, 2019 - ieeexplore.ieee.org
This brief presents a differential time-domain comparator formed by two voltage controlled
delay lines, one per input terminal, and a binary phase detector for comparison solving. The …

Yield Maximization of Flip-Flop Circuits Based on Deep Neural Network and Polyhedral Estimation of Nonlinear Constraints

SA Sajjadi, SA Sadrossadat, A Moftakharzadeh… - IEEE …, 2024 - ieeexplore.ieee.org
In this paper, we propose a method based on deep neural networks for the statistical design
of flip-flops, taking into account nonlinear performance constraints. Flip-flop design and …

Over/undershooting effects in accurate buffer delay model for sub-threshold domain

P Corsonello, F Frustaci, M Lanuzza… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Scaling down the supply voltage (V dd) below the transistors threshold voltage (V th) has
become a very popular technique in designing Ultra-Low-Power circuits whose demand has …