An intelligent adaptive arbiter for maximum CPU utilization, fair bandwidth allocation and low latency
MN Akhtar, O Sidek - IETE Journal of Research, 2013 - Taylor & Francis
Rapid advancement in the world of microprocessor necessitates solving the bus contention
in a most efficient manner. The major challenge is to reduce the latency of the system and to …
in a most efficient manner. The major challenge is to reduce the latency of the system and to …
Towards correct and reusable Network-on-Chip architectures
With network-on-chip (NoC) as the fundamental communication paradigm for many core
architectures, we need to be able to evaluate its correctness. In this paper we propose a …
architectures, we need to be able to evaluate its correctness. In this paper we propose a …
Reusable formal architectures for networked systems
M Kamali - 2013 - doria.fi
Today's networked systems are becoming increasingly complex and diverse. The current
simulation and runtime verification techniques do not provide support for developing such …
simulation and runtime verification techniques do not provide support for developing such …