A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters
A significant challenge in designing high‐speed time‐interleaved ADCs (TI‐ADCs) is the
presence of time skew mismatch, resulting from uneven sampling across different channels …
presence of time skew mismatch, resulting from uneven sampling across different channels …
A 6b 10gs/s ti-sar adc with embedded 2-tap ffe/1-tap dfe in 65nm cmos
A 64-way time-interleaved successive approximation based ADC front-end efficiently
incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits …
incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits …
A 6-b 1.6-GS/s ADC with redundant cycle one-tap embedded DFE in 90-nm CMOS
ADC-BASED serial link receivers are emerging in order to scale data rates over high
attenuation channels. Embedding partial equalization inside the front-end ADC can …
attenuation channels. Embedding partial equalization inside the front-end ADC can …
A 12.8-Gbaud ADC-based wireline receiver with embedded IIR equalizer
JW Nam, MSW Chen - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
This article demonstrates an analog-to-digital converter (ADC)-based receiver for
NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle …
NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle …
A high-speed offset cancelling distributed sample-and-hold architecture for flash A/D converters
L Mountrichas, S Siskos - Microelectronics Journal, 2013 - Elsevier
A 6-bit high-speed analog-to-digital converter was implemented utilizing a novel distributed
sample-and-hold architecture capable of sampling and subtracting the input preamplifier's …
sample-and-hold architecture capable of sampling and subtracting the input preamplifier's …
Switched Current Integrating Sampler for Time Interleaved ADCs
M Ensafdaran, W Namgoong - IEEE Transactions on Circuits …, 2013 - ieeexplore.ieee.org
With the continued improvements in time-interleaved ADC (TIADC) performance, the power
of voltage buffer in input track-and-hold amplifier (THA) driving the ADC input capacitor …
of voltage buffer in input track-and-hold amplifier (THA) driving the ADC input capacitor …
A single parity check forward error correction method for high speed I/O
Some proposed high speed wireline communications make use of an ADC front end to allow
a feedforward equalizer (FFE) to compensate for the frequency dependent loss of the …
a feedforward equalizer (FFE) to compensate for the frequency dependent loss of the …
Design of a 1.5 GSPS 5bit folding and interpolating ADC with distributed S/H folding amplifiers in 90 nm CMOS technology
SL Li, H Hong, S Liu - Industrial Engineering and Management …, 2015 - api.taylorfrancis.com
The Folding and Interpolating Analog to Digital Converters (F&I ADCs) with sampling rate
higher than 1GSPS are widely used in high speed data acquisition, military and avionics …
higher than 1GSPS are widely used in high speed data acquisition, military and avionics …
[图书][B] Design of energy-efficient A/D converters with partial embedded equalization for high-speed wireline receiver applications
EZ Tabasy - 2015 - search.proquest.com
As the data rates of wireline communication links increases, channel impairments such as
skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more …
skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more …
[图书][B] Metastability detection and reduction in high speed ADCs
G Cui - 2014 - search.proquest.com
Comparator metastability is a critical issue in the high speed analog-to-digital converter
(ADC). While much attention is paid to flash ADC metastability because flash ADC is the …
(ADC). While much attention is paid to flash ADC metastability because flash ADC is the …