In this paper we introduce a new approach to the consolidation strategy of a data center that
allows an important reduction in the amount of active nodes required to process a …

The number of gates on a chip is quickly growing toward and beyond the one billion mark.
Keeping all the gates running at the beat of a single or a few rationally related clocks is …

Asynchronous circuit design can result in substantial benefits of reduced power, improved
performance, and high modularity. However, asynchronous design styles are largely …

A test method for asynchronous handshake circuits is presented that is based on
synchronous full-scan techniques. The method adds a synchronous test mode to the circuit …

A synchronous mode as well as a scan mode of operation are added to a large class of
asynchronous circuits, in compliance with LSSD design rules. This enables the application …

A new test method for self-timed circuits is presented that only uses multiplexers to make the
majority of combinational feedback loops testable. Combinational feedback loops are …

Asynchronous design offers a solution to the interconnect problems faced by system-on-chip
(SoC) designers, but their adoption has been held back by a lack of methodology and …

Establishing a general and high-quality testing method for fabricated asynchronous circuits
is crucial for the widespread adoption of asynchronous circuits. A full scan design for …

A globally-asynchronous and locally-synchronous (GALS) system has been known as a
realistic hardware design solution for many difficulties such as global clock network that …

Due to asynchronous timing and arbitration asynchronous designs may behave no
deterministically. For the test of such systems, this means that an exact timing, ie a tester …