Distributed real-time embedded systems: Recent advances, future trends and their impact on manufacturing plant control

CE Pereira, L Carro - Annual Reviews in Control, 2007 - Elsevier
Real-time and embedded systems have historically been small scale. However, advances in
microelectronics and software now allow embedded systems to be composed of a large set …

Binary synthesis

G Stitt, F Vahid - ACM Transactions on Design Automation of Electronic …, 2008 - dl.acm.org
Recent high-level synthesis approaches and C-based hardware description languages
attempt to improve the hardware design process by allowing developers to capture desired …

Transparent acceleration of data dependent instructions for general purpose processors

ACS Beck, L Carro - 2007 IFIP international conference on very …, 2007 - ieeexplore.ieee.org
Although transistor scaling keeps following Moore's law, and more area is available for
designers, the clock frequency and ILP rate do not present the same level of growth …

Towards a multiple-ISA embedded system

J Fajardo Jr, MB Rutzig, L Carro, ACS Beck - Journal of Systems …, 2013 - Elsevier
In these days, every new added hardware feature must not change the underlying
Instruction Set Architecture (ISA), in order to avoid adaptation or recompilation of existing …

Exploring online synthesis for CGRAs with specialized operator sets

S Döbrich, C Hochberger - International Journal of …, 2011 - Wiley Online Library
The design of energy‐efficient systems has become a major challenge for engineers over
the last decade. One way to save energy is to spread out computations in space rather than …

Just-in-time instruction set extension-feasibility and limitations for an fpga-based reconfigurable asip architecture

M Grad, C Plessl - 2011 IEEE International Symposium on …, 2011 - ieeexplore.ieee.org
In this paper, we study the feasibility of moving the instruction set customization process for
reconfigurable ASIPs to runtime under the precondition that current FPGA devices and tools …

Efficient memory management for hardware accelerated java virtual machines

P Bertels, W Heirman, E D'Hollander… - ACM Transactions on …, 2009 - dl.acm.org
Application-specific hardware accelerators can significantly improve a system's
performance. In a Java-based system, we then have to consider a hybrid architecture that …

A java framework to teach computer architecture

RS Ferreira, ACS Beck, L Carro, A Toledo… - New Trends and …, 2005 - Springer
This work proposes a Java-based framework to teach computer architecture design. Our
methodology allows students rapidly to explore many different concepts across multiple …

Thread warping: Dynamic and transparent synthesis of thread accelerators

G Stitt, F Vahid - ACM Transactions on Design Automation of Electronic …, 2011 - dl.acm.org
We introduce thread warping, a dynamic optimization technique that customizes multicore
architectures to a given application by dynamically synthesizing threads into custom …

A multiple-ISA reconfigurable architecture

FM Capella, M Brandalero, L Carro… - Design Automation for …, 2015 - Springer
In these days, every newly added hardware feature must not change the underlying
instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing …