In several digital signal processing algorithms, computational nodes are organized in
consecutive stages and data is reordered between these stages. Parallel computation of …

Aggressive technology scaling down and low-power design techniques lead to uneven
distributed power density, which translates into heat flow in the chips, causing significant …

This Thesis considers systematic methods for designing stride permutation interconnections,
which are common in several digital signal processing algorithms. Managing such …

In this paper, the architecture of a fully pipelined discrete cosine transform (DCT) hardware
accelerator for a JPEG encoder is proposed. The integration of the accelerator into the …

Embedded multimedia systems are expected to fully embrace the future many-core wave. As
a consequence parallel programming is being revamped as the only way to exploit the …

In this paper, we describe the design and implementation of a prototype single chip VLSI
architecture for implementing the JPEG baseline image compression standard. The chip …

In this paper, we present an adaptive agent-based partner selection mechanism for routing
packet in distributed wireless sensor networks. A wireless sensor network is modelled as a …

This paper presents ultra low power implementation of eight-point 2-D DCT (Discrete Cosine
Transform) based on a Loeffler DCT scheme. The proposed implementation scheme does …

This research focuses on the implementation of the efficient image compression system
among the many potential applications of a transform imager system. The study includes …

DSP and particularly multimedia systems are among the most rapidly developing areas of
digital IC (Integrated Circuit) design. Multimedia hardware designers face the same time-to …