Linear temporal logic symbolic model checking

KY Rozier - Computer Science Review, 2011 - Elsevier
We are seeing an increased push in the use of formal verification techniques in safety-
critical software and hardware in practice. Formal verification has been successfully used to …

Monitoring temporal properties of continuous signals

O Maler, D Nickovic - International symposium on formal techniques in …, 2004 - Springer
In this paper we introduce a variant of temporal logic tailored for specifying desired
properties of continuous signals. The logic is based on a bounded subset of the real-time …

[图书][B] Handbook of knowledge representation

F Van Harmelen, V Lifschitz, B Porter - 2008 - books.google.com
Handbook of Knowledge Representation describes the essential foundations of Knowledge
Representation, which lies at the core of Artificial Intelligence (AI). The book provides an up …

[图书][B] On-chip communication architectures: system on chip interconnect

S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

[图书][B] Industrial communication technology handbook

R Zurawski - 2014 - books.google.com
Featuring contributions from major technology vendors, industry consortia, and government
and private research establishments, the Industrial Communication Technology Handbook …

System-on-chip: Reuse and integration

R Saleh, S Wilton, S Mirabbasi, A Hu… - Proceedings of the …, 2006 - ieeexplore.ieee.org
Over the past ten years, as integrated circuits became increasingly more complex and
expensive, the industry began to embrace new design and reuse methodologies that are …

DPLL(T): Fast Decision Procedures

H Ganzinger, G Hagen, R Nieuwenhuis… - … Aided Verification: 16th …, 2004 - Springer
The logic of equality with uninterpreted functions (EUF) and its extensions have been widely
applied to processor verification, by means of a large variety of progressively more …

[图书][B] A practical introduction to PSL

C Eisner, D Fisman - 2007 - books.google.com
Functional veri? cation is hard. Period. No disagreement here. But why is this so? Consider
today's design? ow: much of it is more or less automated, from RTL to netlist to layout to …

The ForSpec temporal logic: A new temporal property-specification language

R Armoni, L Fix, A Flaisher, R Gerth, B Ginsburg… - … Conference on Tools …, 2002 - Springer
In this paper we describe the ForSpec Temporal Logic (FTL), the new temporal property-
specification logic of ForSpec, Intel's new formal specification language. The key features of …

Applying model checking to industrial-sized PLC programs

BF Adiego, D Darvas, EB Viñuela… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
Programmable logic controllers (PLCs) are embedded computers widely used in industrial
control systems. Ensuring that a PLC software complies with its specification is a challenging …