Scalable construction of approximate multipliers with formally guaranteed worst case error

V Mrazek, Z Vasicek, L Sekanina… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Approximate computing exploits the fact that many applications are inherently error resilient.
In order to reduce power consumption, approximate circuits such as multipliers have been …

Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished

M Češka, J Matyáš, V Mrazek… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
We present a novel method allowing one to approximate complex arithmetic circuits with
formal guarantees on the approximation error. The method integrates in a unique way formal …

Formal methods for exact analysis of approximate circuits

Z Vasicek - IEEE Access, 2019 - ieeexplore.ieee.org
Approximate circuits are digital circuits that are intentionally designed in such a way that the
specification is violated in terms of functionality in order to obtain some improvements in …

Automated search-based functional approximation for digital circuits

L Sekanina, Z Vasicek, V Mrazek - Approximate Circuits: Methodologies …, 2019 - Springer
The problem of developing an approximate implementation of a given combinational circuit
can be formulated as a multi-objective design problem and solved by means of a search …

Adaptable approximate multiplier design based on input distribution and polarity

Z Li, S Zheng, J Zhang, Y Lu, J Gao… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Approximate computing is an efficient approach to reduce the design complexity for error-
resilient applications. Multipliers are key arithmetic units in many applications, such as deep …

Efficient 2D DCT architecture based on approximate compressors for image compression with HEVC intra-prediction

A Akman, S Cekli - Journal of Real-Time Image Processing, 2023 - Springer
This study presents a design of two-dimensional (2D) discrete cosine transform (DCT)
architecture to be used with high-efficiency video coding (HEVC) intra-prediction method in …

Relaxed equivalence checking: a new challenge in logic synthesis

Z Vasicek - 2017 IEEE 20th International Symposium on …, 2017 - ieeexplore.ieee.org
The functional equivalence has always been the integral part of virtually every logic
synthesis tool. The formal equivalence checking represents a key process that helps logic …

AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization

Z Li, H Zhou, L Wang, X Zhou - 2023 International Conference …, 2023 - ieeexplore.ieee.org
We propose AMG, an open-source automated approximate multiplier generator for FPGAs
driven by Bayesian optimization (BO) with parallel evaluation. The proposed method …

Video coding and processing: a survey

Y Liu, S Liu, Y Wang, H Zhao - Neurocomputing, 2020 - Elsevier
Vision is the main way for people to perceive and recognize the world. In this paper, four
categories of the redundant information of video encoding, spatial redundancy, time …

Formal probabilistic analysis of low latency approximate adders

A Qureshi, O Hasan - … on computer-aided design of integrated …, 2018 - ieeexplore.ieee.org
Approximate computing is an emerging trend in hardware and software design that
leverages upon the inherent tolerance for inaccuracy in applications to optimize their power …